sgherbst

svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

svinst

Determines the modules declared and instantiated in a SystemVerilog file

msdsl

Automatic generation of real number models from analog circuits

anasymod

A framework for FPGA emulation of mixed-signal systems

sky130-hello-world

Minimal SKY130 example with self-checking LVS, DRC, and PEX

pysvinst

Python library for parsing module definitions and instantiations from SystemVerilog files

pyhigh

Python library for accessing elevation data

tapdance

JTAG debug generator written in magma

jtag_test

Fully-automated Vivado + SDK example that tests an emulated JTAG TAP controller

champ

Channel modeling in Python

cs229-project

Real-time analysis of fruit-fly videos

fault_experiments

FreeRouting

Printed Circuit Board Routing Software from FreeRouting.net

hslink-emu

Event-driven FPGA emulation model of a high-speed link

PyPDF2

A utility to read and write PDFs with Python

buck-emu

eqtest

nodeville

pycap

yogurtrice

Yogurt maker built from a rice cooker

fixture_demo_kiwi

kicad-python

Development of a new Python scripting API for KiCad

Python-PCB

Python PCB autorouter

simple-base-lib

SkyPHY

slang

SystemVerilog compiler and language services

svinst-slang