There are 2 repositories under nmigen topic.
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
assorted library of utility cores for amaranth HDL
An experiment for building gateware for the axiom micro / beta using amaranth-hdl
A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
a USB2 highspeed device core, written in amaranth HDL
A simple (audio) synthesizer on the iCEBreaker FPGA.
command line tool for frequent amaranth HDL tasks (generate sources, show design)
Up-to-date board and connector definition files for amaranth HDL
A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91
nMigen - version 1 - A refreshed Python toolbox for building complex digital hardware - MIRRORED - https://gitlab.com/nmigen/nmigen
nyanMigen: pretty face for nMigen (https://github.com/nmigen/nmigen)
Board and connector definition files for nMigen - MIRRORED - https://gitlab.com/nmigen/nmigen-boards/
nmigen-soc - System on Chip toolkit for nMigen - MIRRORED - https://gitlab.com/nmigen/nmigen-soc/
nmignen-stdio - Industry standard I/O for nMigen - MIRRORED - https://gitlab.com/nmigen/nmigen-stdio/
This is me playing around with my new Icebreaker FPGA with nmigen(_dg). The goal is to find a nice project structure and perhaps find a way to work on my arty a7 with a FOSS toolchain
Examples for the Chubby Hat FPGA Development platform
Simple RISC-V (RV32I) soft CPU implementation using nMigen and Verilog