MicroDynamics CPU's repositories
tree-core-ide
:deciduous_tree: The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
tree-core-cpu
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
tree-core-ip
A series of IP which has cycle-accurate, event-driven simulation models.
tree-core-compiler
zodiac: A tiny statically typed, compiled system programming language which supports many modern features to build reliable and efficient software.
tree-core-asic
An Universal Simulation and Verification Environment for ASIC.
tree-core-backend
A core component of TreeCore IDE to execute heavy computing task in backstage.
tree-core-fpga
An Universal FPGA Framework for SoC Simulation and Verification
tree-core-os
A unix-like operating system written in zodiac lang.
tree-core-sim
A lightweight cloudFPGA prototype for processor simulation. It provides online scalable route resources with only open source synthesis toolset.
tree-core-soc
A verilator based SoC simulation framework for TreeCore CPU.
tree-core-website
This is the website of treecore project.
backend-design-tutorial
This is the tutorial for chip backend design lab by using all open-source toolsets.
tree-core-bus
A General Bus Generator which supporting AMBA, Wishbone, TileLink and ChipLink.
tree-core-cicd
A CI/CD environment for the processor simulation and verification.
tree-core-cpu-res
This is the resources folder of the treecore cpu.
tree-core-ide-res
This is the resources folder of the treecore ide.
tree-core-ide-tutorial
This is the tutorial for TreeCore IDE usage.
tree-core-rtos
a simple real-time operation system implement in C which support riscv ISA.
tree-core-sim-res
This is the resources folder of the treecore sim.
tree-core-test
A Software Test Sets for Processor Simulation and Verification