MicroDynamics CPU (microdynamics-cpu)

MicroDynamics CPU

microdynamics-cpu

Geek Repo

Create free, easy-to-use RSIC-V processors and development environment.

Location:Beijing, China

Home Page:https://treecore.xyz

Github PK Tool:Github PK Tool

MicroDynamics CPU's repositories

tree-core-ide

:deciduous_tree: The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Language:JavaScriptLicense:GPL-3.0Stargazers:98Issues:8Issues:2

tree-core-cpu

:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Language:ScalaLicense:GPL-3.0Stargazers:36Issues:6Issues:0

tree-core-ip

A series of IP which has cycle-accurate, event-driven simulation models.

Language:SystemVerilogLicense:GPL-3.0Stargazers:4Issues:2Issues:0

tree-core-compiler

zodiac: A tiny statically typed, compiled system programming language which supports many modern features to build reliable and efficient software.

Language:RustLicense:GPL-3.0Stargazers:3Issues:2Issues:0

tree-core-asic

An Universal Simulation and Verification Environment for ASIC.

Language:VerilogLicense:GPL-3.0Stargazers:2Issues:0Issues:0

tree-core-backend

A core component of TreeCore IDE to execute heavy computing task in backstage.

Language:RustLicense:GPL-3.0Stargazers:2Issues:0Issues:0

tree-core-fpga

An Universal FPGA Framework for SoC Simulation and Verification

Language:VerilogLicense:GPL-3.0Stargazers:2Issues:2Issues:0

tree-core-os

A unix-like operating system written in zodiac lang.

License:GPL-3.0Stargazers:2Issues:0Issues:0

tree-core-sim

A lightweight cloudFPGA prototype for processor simulation. It provides online scalable route resources with only open source synthesis toolset.

Language:C++License:GPL-3.0Stargazers:2Issues:2Issues:0

tree-core-soc

A verilator based SoC simulation framework for TreeCore CPU.

Language:VerilogLicense:NOASSERTIONStargazers:2Issues:0Issues:0

tree-core-website

This is the website of treecore project.

Language:CSSLicense:GPL-3.0Stargazers:2Issues:2Issues:0
License:GPL-3.0Stargazers:1Issues:0Issues:0

backend-design-tutorial

This is the tutorial for chip backend design lab by using all open-source toolsets.

License:GPL-3.0Stargazers:1Issues:2Issues:0

tree-core-bus

A General Bus Generator which supporting AMBA, Wishbone, TileLink and ChipLink.

Language:CLicense:GPL-3.0Stargazers:1Issues:2Issues:0

tree-core-cicd

A CI/CD environment for the processor simulation and verification.

Language:PythonLicense:GPL-3.0Stargazers:1Issues:2Issues:0

tree-core-cpu-res

This is the resources folder of the treecore cpu.

License:GPL-3.0Stargazers:1Issues:2Issues:0

tree-core-ide-res

This is the resources folder of the treecore ide.

License:GPL-3.0Stargazers:1Issues:3Issues:0

tree-core-ide-tutorial

This is the tutorial for TreeCore IDE usage.

License:GPL-3.0Stargazers:1Issues:0Issues:0
Language:CLicense:GPL-3.0Stargazers:1Issues:0Issues:0

tree-core-rtos

a simple real-time operation system implement in C which support riscv ISA.

License:GPL-3.0Stargazers:1Issues:0Issues:0
License:GPL-3.0Stargazers:1Issues:0Issues:0

tree-core-sim-res

This is the resources folder of the treecore sim.

License:GPL-3.0Stargazers:1Issues:0Issues:0

tree-core-test

A Software Test Sets for Processor Simulation and Verification

Language:CLicense:GPL-3.0Stargazers:1Issues:0Issues:0