chipyard

There are 1 repository under chipyard topic.

ucb-bar / chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rocket-chip chip-generator chisel riscv rtl soc peripherals chipyard risc-v boom firesim hwacha accelerators rocket out-of-order superscalar
Language:C 1412
firesim / FireMarshal
Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
firesim qemu spike distro workload linux buildroot fedora chipyard
Language:Python 67
mit-ll / CEP
The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
riscv verilog risc-v fpga rocket-chip osh oshw soc chipyard
Language:C 56
MaxXSoft / Bossa
BOOM's Simulation Accelerator.
boom rocket rocket-chip simulation chipyard accelerator chisel riscv risc-v rtl soc verilator firrtl
Language:Scala 10
RedFlag2017 / rocket-soc-tb
A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs
risc-v chipyard testbech soc verifcation
Language:Verilog 7
ThePituLegend / RISC-V_DE10-Nano
This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.
riscv risc-v riscv64 riscv-asm riscv-assembly de10-nano fpga altera altera-fpga terasic rocketchip chipyard ucberkeley
Language:Verilog 7
Fleker / chipyard-viewer
An online viewer for Chipyard output files
hacktoberfest system-on-chip chipyard webapp
Language:TypeScript 5
Kian75 / Chisel_Examples
chisel3 rtl chipyard fpga risc-v
Language:Scala 1

chipyard

ucb-bar / chipyard

firesim / FireMarshal

mit-ll / CEP

MaxXSoft / Bossa

RedFlag2017 / rocket-soc-tb

ThePituLegend / RISC-V_DE10-Nano

Fleker / chipyard-viewer

Kian75 / Chisel_Examples