There are 3 repositories under hardware-verification topic.
CoreIR Symbolic Analyzer
This repo is created to include illustrative examples on object oriented design pattern in SV
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
Specman/e-language syntax for Sublime Text 3
This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.
Through a verification environment, this repository uses UVM to handle with multiple clock domains and virtual sequences.
About Coursework 2 for ELEC70056: Hardware and Software Verification, Hardware Component - Verification of SystemVerilog designs using assertions and timing statements