out-of-order

There are 0 repository under out-of-order topic.

ucb-bar / chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rocket-chip chip-generator chisel riscv rtl soc peripherals chipyard risc-v boom firesim hwacha accelerators rocket out-of-order superscalar
Language:Scala 2026
RRZE-HPC / OSACA
Open Source Architecture Code Analyzer
hpc performance-analysis performance-modeling in-core x86 arm64v8 sve avx avx2 avx512 port-mapping out-of-order throughput latency loop-carried-dependency critical-path assembly python aarch64 neon
Language:Jupyter Notebook 337
mathis-s / SoomRV
A simple superscalar out-of-order RISC-V microprocessor
computer-architecture cpu ooo out-of-order risc-v systemverilog
Language:SystemVerilog 224
riscv-software-src / riscv-perf-model
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
modeling out-of-order performance-analysis risc-v
Language:C++ 189
NOP-Processor / NOP-Core
High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
loongarch out-of-order processor spinalhdl loongarch32r
Language:Scala 82
sifferman / labs-with-cva6
Advanced Architecture Labs with CVA6
branch-prediction caching cva6 education out-of-order risc-v systemverilog virtual-memory
Language:SystemVerilog 70
bcrafton / processor
A compiler, assembler, and processor.
assembler processor memory-simulator compiler superscalar out-of-order branch-predictor performance os simd
Language:OCaml 24
NoAXI-LoongArch-CPU
NoAXI / NoAXI-LoongArch-CPU
Second Prize in NSCSCC 2024. Out-of-order CPU design from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品
cpu loongarch32r out-of-order
Language:Scala 20
SIMDE-ULL / SIMDE
Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals
simulator educational computer-architecture out-of-order computer-architecture-and-organization instruction-level-parallelism learning-by-doing learning-resources pipelining risc superscalar
Language:TypeScript 13
DataSystemsGroupUT / Adaptive-Watermarks
An approach to apply concept drifts and ADWIN on the streams event time to reason about the progress of watermarks
adwin flink-streaming out-of-order stream-processing watermark
Language:Java 11
RISMicroDevices / RMM4NC30F2X
Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
mips32 out-of-order axi4 fpga fpga-soc high-frequency nscscc2022 nscscc2022-single
Language:VHDL 11
RISMicroDevices / RMR8PM3001A
Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC
risc-v rv64 verilog verilog-project verilator out-of-order ysyx3 ysyx4 rv64i jasse
Language:C++ 9
CSpyridakis / Tomasulo
Introduction in Dynamic Instruction Scheduling (Advanced Computer Architecture) implementing Tomasulo's Algorithm
tomasulo vhdl computer-architecture architecture instruction-level-parallelism out-of-order tomasulo-algorithm pipeline-processor pipeline
Language:VHDL 4
TawfikYasser / Keyed-Watermarks-in-Apache-Flink
Keyed Watermarks in Apache Flink
bash flink flink-streaming java linux python keyed-watermarks out-of-order stream-processing
Language:Java 4
0mega28 / CPU-Simulator
CENOS: The Modern CPU Simulator
cpu-simulation out-of-order scoreboarding-algorithm pipeline-processor 2-pass-assembler branch-prediction simulator
Language:C++ 3
mark-i-m / riscy
Superscalar OoO RISCV processor written in Chisel
riscv out-of-order core processor superscalar chisel
Language:Scala 3
wh1t3h47 / EdgeMailer
EdgeMailer is a tool that tests rate limits of mail providers, it uses libcurl and libuv to make concomitant assynchronous request. This tool is outdated and now is closed source and belongs to YouSendr.
c mass-requests pentesting pentest private-repository public-mirror outdated libev libuv libcurl event-loop assynchronous out-of-order makefile automake
Language:C 3
agarwal-ayushi / HPC_Labs
This repository contains the Labs done in the course COL718 High Performance Computing taught by Prof. Sourav Bansal at IIT, Delhi in Fall 2019
high-performance-computing cache computer-architecture spec cpu2017 out-of-order
Language:C++ 2
DataSystemsGroupUT / Process-Discovery-over-unordered-streams
A Flink library to implement both a buffer-based and a speculative out-of-order event arrival handlers for online process discovery
process-mining data-stream-processing out-of-order
Language:Java 2
gitmehrdad / Superscalar-MIPS
This Verilog implementation represents a 32-bit MIPS processor featuring out-of-order execution.
mips mips32 processor-architecture superscalar out-of-order pipeline
Language:Verilog 2
noionion / KaiSui
try to design a Single_Emission_Out-of-Order_Pipeline_RISC-V_Processor
cpu out-of-order risc-v rv64im
Language:Verilog 2
pranav0x0112 / Specula
Specula is a dual-issue, out-of-order RISC-V RV32I core featuring basic dynamic scheduling and register renaming. Designed for simulation (WIP)
bluespec-systemverilog risc-v computer-architecture out-of-order
Language:Bluespec 2
AyuubMohamud / Biriq
2-way Out of Order RISC-V Processor
cpu embedded out-of-order risc-v riscv
Language:C 1
helcsnewsxd / microarch-design-impact
Microarchitecture impact analysis using gem5 - Computer Architecture course project - Computer Science @ FAMAF (UNC)
analysis armv8 assembly c hardware-description-language in-order-pipeline-architecture lab optimization out-of-order pipelined-processors processor processor-architecture processor-simulation python qemu quartus system-verilog university-project famaf gem5
Language:Assembly 1
vbogdev / vbn-Riscv
An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.
axi4 ddr3 fpga out-of-order processor processor-architecture processor-design processor-simulator risc-v superscalar superscalar-cpu
Language:SystemVerilog 1
wdamron / bitring
Go implementation of a bitmap ring-buffer which tracks the state of windowed out-of-order processing over a sequence of logical offsets
bitmap ring-buffer circular-buffer out-of-order windowed
Language:Go 1
Amutheezan / Tomasulo
Basic Implementation of Tomasulo Algorithm, with memory unit pipelined.
tomasulo-algorithm out-of-order
Language:Python 0
zhuangsc / RFC_marss86
Register file cache implementation on the Marssx86 architectural simulator
microarchitecture out-of-order cpu-simulator computer-architecture
Language:C 0

out-of-order

ucb-bar / chipyard

RRZE-HPC / OSACA

mathis-s / SoomRV

riscv-software-src / riscv-perf-model

NOP-Processor / NOP-Core

sifferman / labs-with-cva6

bcrafton / processor

NoAXI / NoAXI-LoongArch-CPU

SIMDE-ULL / SIMDE

DataSystemsGroupUT / Adaptive-Watermarks

RISMicroDevices / RMM4NC30F2X

RISMicroDevices / RMR8PM3001A

CSpyridakis / Tomasulo

TawfikYasser / Keyed-Watermarks-in-Apache-Flink

0mega28 / CPU-Simulator

mark-i-m / riscy

wh1t3h47 / EdgeMailer

agarwal-ayushi / HPC_Labs

DataSystemsGroupUT / Process-Discovery-over-unordered-streams

gitmehrdad / Superscalar-MIPS

noionion / KaiSui

pranav0x0112 / Specula

AyuubMohamud / Biriq

helcsnewsxd / microarch-design-impact

vbogdev / vbn-Riscv

wdamron / bitring

Amutheezan / Tomasulo

zhuangsc / RFC_marss86