rocket-chip

There are 1 repository under rocket-chip topic.

chipsalliance / rocket-chip
Rocket Chip Generator
scala rocket-chip chip-generator chisel riscv rtl
Language:Scala 3377
riscv-boom / riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
riscv boom chisel rtl rocket-chip scala riscv-boom berkeley
Language:Scala 1838
ucb-bar / chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rocket-chip chip-generator chisel riscv rtl soc peripherals chipyard risc-v boom firesim hwacha accelerators rocket out-of-order superscalar
Language:Scala 1776
firesim
firesim / firesim
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
boom cloud datacenter firesim fpga hardware on-prem risc-v rocket-chip simulation
Language:Scala 912
bu-icsg / dana
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
neural-network rocket-chip hardware riscv rtl chisel rocc
Language:Scala 210
eliaskousk / parallella-riscv
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
gsoc gsoc-2016 linux-kernel parallella petalinux risc-v rocket-chip rocket-core zedboard zynq
Language:SystemVerilog 100
seldridge / rocket-rocc-examples
Tests for example Rocket Custom Coprocessors
riscv rocket-chip rocc
Language:C 70
mit-ll / CEP
The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
riscv verilog risc-v fpga rocket-chip osh oshw soc chipyard
Language:C 64
li3tuo4 / rc-fpga-zcu
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
fpga-board linux-boot risc-v rocket-chip vivado zcu102 zynqmp
Language:Tcl 59
firesim / firechip
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
risc-v rocket-chip soc
Language:C 56
IBM / rocc-software
C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
riscv rocket-chip rocc
Language:C 52
IBM / chiffre
A fault-injection framework using Chisel and FIRRTL
chisel firrtl risc-v rocc rocket-chip fault-injection
Language:Scala 34
hex-five / multizone-fpga
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.
risc-v rocket-chip fpga fpga-soc xilinx xilinx-fpga e300 bitstream digilent sifive-freedom arty-a7 artix-35t artix-100t sifive
Language:Scala 29
jiegec / rocket-chip-vcu128
Run Rocket Chip on VCU128
risc-v rocket-chip vcu128
Language:Tcl 29
esperantotech / boom-template
A template for building new projects/platforms using the BOOM core.
boom chisel riscv rocket-chip rtl scala
Language:Shell 24
firesim / icenet
Network components (NIC, Switch) for FireBox
nic network chisel rocket-chip risc-v
Language:Scala 16
MaxXSoft / Bossa
BOOM's Simulation Accelerator.
boom rocket rocket-chip simulation chipyard accelerator chisel riscv risc-v rtl soc verilator firrtl
Language:Scala 13
noureddine-as / riscv-baremetal-DefaultConfig
A simple baremetal program template for RISC-V inspired from riscv benchmark tests
risc-v riscv-sim rocket-chip
Language:C 10
UCTECHIP / rocket_chip_vpu
rvv vpu rocket-chip scala chisel
Language:Scala 10
eliaskousk / parallella-riscv-images
Parallella RISC-V Prebuilt Images
parallella board-parallella risc-v rocket-chip zedboard zynq linux-kernel gsoc gsoc-2016
8
yasnakateb / ChipyardIntegration
😱 RoCC Accelerator Integration with Chipyard
accelerators chipyard chisel chisel3 computer-architecture hardware hardware-acceleration integration risc-v rocc rocket rocket-chip sbt scala simulation verilator
3
zhangshuai-neu / rocket_annotate
Annotate rocket-chip
annotate rocket-chip
Language:Scala 1
cepdnaclk / e19-4yp-RISC-V-Based-ASIP-for-Accelerating-DNA-Sequence-Alignment-on-Embedded-Systems
RISC-V based application-specific instruction set processor (ASIP) for Minimap2
asip dna-sequence-alignment embedded-systems fpga hardware-acceleration minimap2 risc-v rocket-chip third-generation-sequencing bioinformatics-acceleration genomic-computing

rocket-chip

chipsalliance / rocket-chip

riscv-boom / riscv-boom

ucb-bar / chipyard

firesim / firesim

bu-icsg / dana

eliaskousk / parallella-riscv

seldridge / rocket-rocc-examples

mit-ll / CEP

li3tuo4 / rc-fpga-zcu

firesim / firechip

IBM / rocc-software

IBM / chiffre

hex-five / multizone-fpga

jiegec / rocket-chip-vcu128

esperantotech / boom-template

firesim / icenet

MaxXSoft / Bossa

noureddine-as / riscv-baremetal-DefaultConfig

UCTECHIP / rocket_chip_vpu

eliaskousk / parallella-riscv-images

yasnakateb / ChipyardIntegration

zhangshuai-neu / rocket_annotate

cepdnaclk / e19-4yp-RISC-V-Based-ASIP-for-Accelerating-DNA-Sequence-Alignment-on-Embedded-Systems