cpu-architecture

There are 2 repositories under cpu-architecture topic.

arm-university / Introduction-to-Computer-Architecture-Education-Kit
Gain an understanding of the fundamental topics and concepts of computer architecture including the application of these with modern Arm processors
arm computer-architectures armv8 computer-engineering cortex-a cpu-architecture electrical-engineering hardware-design
Language:HTML 290
arm-university / Fundamentals-of-System-on-Chip-Design-on-Arm-Cortex-M-Microcontrollers
A textbook on understanding system on chip design
amba arm-cortex-m fpga fpga-soc soc-design system-on-chip-design cmsis cpu-architecture embedded-systems trustzone bus-architecture soc textbook
51
alirezakay / RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
cpu cpu-model cpu-architecture processor-design processor-architecture mips-processor isa instruction-set-architecture multi-cycle risc-processor vhdl vhdl-code vhdl-modules
Language:VHDL 29
MaorAssayag / Architecture-of-CPU-projects
VHDL , ModelSIM, Quartus, FPGA, Image Processing
vhdl cpu-architecture modelsim quartus fpga
Language:VHDL 17
RossComputerGuy / SherwoodArch
The Sherwood Architecture is a custom 64-Bit RISC based CPU architecture.
virtual-machine emulator cpu-emulator cpu computer-architecture assembler sherwood-architecture cpu-architecture architecture
Language:CSS 15
laskarelias / upatras-riscv
Μια ενδεικτική υλοποίηση RISC-V επεξεργαστή και ενός υποστηρικτικού Assembler - Διπλωματική εργασία στο Τμήμα Μηχανικών Η/Υ και Πληροφορικής, Πανεπιστήμιο Πατρών / An Indicative RISC-V CPU Implementation and an Accompanying Assembler - Master's Diploma Thesis at the Computer Engineering and Informatics Department (CEID), University of Patras
risc-v assembler verilog bison-flex cpu-architecture
Language:TeX 7
AkhilRai28 / ALUBuilder
A Verilog project for designing an Arithmetic Logic Unit (ALU) using pre-existing logic blocks. This ALU performs fundamental operations such as addition, subtraction, and logical shifts in a CPU architecture.
alu arithmetic-coding arithmetic-logic-unit cpu cpu-architecture digital-design hardware logic-circuit verilog
4
JimCownie / CpuFun
Code snippets for the CpuFun blog
aarch64 compiler cpu-architecture macos openmp x86-64
Language:C++ 3
MIPT-ILab / MDSP
[2009 – 2012] MDSP: functional simulation of a Multimedia Digital Signal Processor
mdsp mips intel-lab performance-simulation computer-science cpu cpu-architecture microarchitecture
Language:C++ 3
uros-bojanic / 8-bit-computer
[Computer Engineering] Programmable 8-bit computer based on von Neumann architecture, designed and implemented from scratch in Logisim.
logisim cpu-architecture von-neumann-architecture instruction-decoding
3
amari-calipso / custom-emulated-computer
A 16-bit computer architecture i made, emulated in opal
16-bit 16bit cpu cpu-architecture cpu-emulator cpu-emulators custom-cpu emulation emulator sound-card sound-chips sound-processing synthesizer
Language:Opal 2
codehasan / MyArch
📱 An app to view all supported ABI of the running device
abi android cpu-architecture
Language:Java 2
eomielan / 16-bit-RISC-machine
16-bit CPU architecture implementation and verification using SystemVerilog
systemverilog verilog cpu-architecture
2
erwanregy / Cache-Simulation
CPU Cache Simulation using gem5
cache-simulation cpu-architecture cpu-simulation gem5 python
Language:C 2
Kammann123 / ev21g1
General purpose processor with a RISC architecture and a five stage pipeline, implemented on a Cyclone IV FPGA using a development board
fpga de0-nano cpu-architecture architecture cpu verilog hdl
Language:Verilog 2
MartinBrugnara / archetypum
Tomasulo algorithm visualizer
visualization tomasulo cpu-architecture
Language:TypeScript 2
ScheCPUEmulator
schemil053 / ScheCPUEmulator
This is a simple CPU emulator with custom architecture
cpu-architecture cpu-emulator java java-cpu learning-by-doing cpu-architecture-design java-cpu-emulator
Language:Java 2
cedrickchee / nand2tetris
Solutions for http://www.nand2tetris.org/
assembly computer-science computer-systems nand2tetris nand2tetris-assignments cpu-architecture emulator-development logic-gates virtual-machine hack-computer hack-binary
Language:Hack 1
denishoornaert / SimpleSoftcoreArchitecture
cpu-architecture hardware-description-language softcore vhdl
Language:VHDL 1
erwanregy / NoC-Simulation
Network-on-Chip Simulation using Noxim
cpu cpu-architecture network-on-chip noc noxim simulation
Language:Python 1
ewpratten / Dirobium
The virtual CPU (and emulator) built for hobbyists
dirobium cpu-architecture assembly
Language:Python 1
Haaris-RTL / 8-bit-CPU
RTL code of an 8-bit CPU designed in Verilog.
computer-architecture cpu-architecture rtl-design verilog-hdl learning-by-doing personal-project testbench-verification
Language:Verilog 1
MEESAM749 / RISC-V-PipelinedProcessor
RISC-V Pipelined Processor simulation in Verilog on Xilinx ISE
risc-v verilog xilinx-ise cpu cpu-architecture cpu-architecture-design
Language:HTML 1
MEESAM749 / Single-Cycle-Non-Pipelined-MIPS-32-Processor
This is a simulation of the MIPS32 Single Cycle Processor on Xilinx ISE written in Verilog.
cpu cpu-architecture cpu-architecture-design fpga-programming xilinx-ise
Language:C 1
onegentig / VUT-FIT-INP2022-projekt1
První projekt (CPU s brainfuck-like ISA) z předmětu Návrh počítačových systémů (INP), třetí semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023
university-project vhdl vhdl-code vhdl-coursework vut-fit vutbr brno-university-of-technology fpga brainfuck brainlove isa processor-architecture cpu cpu-architecture cpu-simulator microcontroller inp vut
Language:VHDL 1
Sayemum / CS261-Y86-CPU-Simulator
My semester-long project for CS261 - Computer Systems at James Madison University where I constructed a cpu simulator using a smaller version of x86 called y86.
assembly-language computer-systems cpu cpu-architecture debugging elf elf-header testing-tools y86-64 command-line gdb vim visual-studio-code
Language:C 1
SexySparrow / RISC_V
RISC-V CPU arhitecture
risc-v verilog cpu-architecture
Language:Verilog 1
arinaivanova / logisim-cpu
WIP: CPU implemented in LogiSim from NAND gates.
cpu cpu-architecture logisim
0
DebasishPanda529 / EE309_IITB-RISC
Github repo containing all the VHDL files for the EE309 course project involving designing a 16-bit, 6-staged pipelined processor based on the RISC ISA.
cpu-architecture vhdl
Language:VHDL 0
mohdfahad12328 / scpu
a smiple 8bit cpu implemented in verilog and tested on FPGA for understanding how CPU works
cpu cpu-architecture fpga instruction-set-architecture verilog
Language:Verilog 0
simon-gardier / cpu-design
📟 32 bits CPU design
cpu cpu-architecture harvard-architecture info0012
Language:Python 0
ThiagoDSMarcelino / cpu-architecture
16-bit CPU with specific Assembler for Assembly codes capable of controlling a 32x32 led screen
16-bit cpu-architecture logisim-cpu
Language:C# 0
Hridxyz / Microprocessor-Assembly-Language
A repository of my assembly language learning journey, featuring programs that illustrate the core principles of microprocessor operations and low-level coding.
assembly-language computer-architecture cpu-architecture low-level-programming microprocessor
Language:Assembly
Mariuspersen / cisc64
Idea for a new type of architecture
cpu-architecture instruction-set instruction-set-architecture
Language:Zig
p4ulor / Eletronics-n-Computer-Design
🔌 Electronics, logic dates, digital circuits & CPU design/architecture. ISEL college subjects: LSD, AC, LIC
ac cpu-architecture digital-circuits isel logic-gates lsd
Language:Assembly
ParkerTenBroeck / MyCPU_16bit
A 16 bit SAP-1 CPU that I designed in grade 10 designed in logisim
cpu cpu-architecture logisim

cpu-architecture

arm-university / Introduction-to-Computer-Architecture-Education-Kit

arm-university / Fundamentals-of-System-on-Chip-Design-on-Arm-Cortex-M-Microcontrollers

alirezakay / RISC-CPU

MaorAssayag / Architecture-of-CPU-projects

RossComputerGuy / SherwoodArch

laskarelias / upatras-riscv

AkhilRai28 / ALUBuilder

JimCownie / CpuFun

MIPT-ILab / MDSP

uros-bojanic / 8-bit-computer

amari-calipso / custom-emulated-computer

codehasan / MyArch

eomielan / 16-bit-RISC-machine

erwanregy / Cache-Simulation

Kammann123 / ev21g1

MartinBrugnara / archetypum

schemil053 / ScheCPUEmulator

cedrickchee / nand2tetris

denishoornaert / SimpleSoftcoreArchitecture

erwanregy / NoC-Simulation

ewpratten / Dirobium

Haaris-RTL / 8-bit-CPU

MEESAM749 / RISC-V-PipelinedProcessor

MEESAM749 / Single-Cycle-Non-Pipelined-MIPS-32-Processor

onegentig / VUT-FIT-INP2022-projekt1

Sayemum / CS261-Y86-CPU-Simulator

SexySparrow / RISC_V

arinaivanova / logisim-cpu

DebasishPanda529 / EE309_IITB-RISC

mohdfahad12328 / scpu

simon-gardier / cpu-design

ThiagoDSMarcelino / cpu-architecture

Hridxyz / Microprocessor-Assembly-Language

Mariuspersen / cisc64

p4ulor / Eletronics-n-Computer-Design

ParkerTenBroeck / MyCPU_16bit