tharinduSamare

Multicore_processor_verilog_design

This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.

Code-compression

Code compression and decompression with 8 methods using frequency based dictionary.

HINet

learn_chisel

Multicore_processor_SystemVerilog_design

This is a multicore processor specially designed for matrix multiplication.

RISCV_processor_design

This is a RISC-V 32I processor which also supports the M extension.

UVM_switch_test

This is a UVM test bench for a simple combinational switch, designed for learning purposes.

PIC_workshop

tharinduSamare