Tharindu Samarakoon's repositories
Multicore_processor_verilog_design
This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.
Code-compression
Code compression and decompression with 8 methods using frequency based dictionary.
Language:PythonNOASSERTION000
Language:ScalaUnlicense000
Multicore_processor_SystemVerilog_design
This is a multicore processor specially designed for matrix multiplication.
Language:SystemVerilog000
RISCV_processor_design
This is a RISC-V 32I processor which also supports the M extension.
Language:SystemVerilog000
UVM_switch_test
This is a UVM test bench for a simple combinational switch, designed for learning purposes.
Language:SystemVerilog000
Language:Makefile000