questasim

There are 1 repository under questasim topic.

suoto / hdl_checker
Repurposing existing HDL tools to help writing better code
vhdl modelsim xilinx verilog systemverilog python hdl xilinx-vivado syntax-checker lsp-server vivado-simulator ghdl vim hdl-checker language-server coc-nvim questasim mentor-msim vim-ale emacs-lsp
Language:Python 217
Paebbels / JSON-for-VHDL
A JSON library implemented in VHDL.
vhdl json parser fileformat fpga xilinx lattice modelsim questasim ghdl simulation synthesis
Language:VHDL 79
MJoergen / HyperRAM
Portable HyperRAM controller
hyperram xilinx vivado artix fpga vhdl avalon intel altera lattice quartus modelsim questasim questa
Language:VHDL 60
Ghonimo / Pre_Silicon-AHB-to_APB-Verification
Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
digital-design questasim semiconductor simulation systemverilog testbench uvm uvm-verification verification verification-methodologies vip ahb2apb
Language:SystemVerilog 38
wyvernSemi / mem_model
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
avalon axi cosimulation dpi-c ghdl memory-model nvc pli questasim simulation test-bench verilator verilog verilog-components verilog-testbenches vhdl vivado-simulator
Language:VHDL 25
NikLeberg / cosim_jtag
Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.
cosimulation gdb ghdl jtag openocd vhdl vhpi fli modelsim nvc questasim
Language:C 14
htminuslab / Modelsim-Unicorn
Modelsim QEMU Unicorn integration via the FLI
emulator fli modelsim questasim risc-v vhdl
Language:C 13
MJoergen / Avalon
Utilities for Avalon Memory Map
avalon fpga intel altera xilinx vivado quartus modelsim questasim questa memory
Language:VHDL 9
Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
questasim rtl rtl-design testbench verilog vivado finite-state-machine synthesis systemverilog
Language:Verilog 8
Noamv7 / Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
chip-design logic-design sva systemverilog verification verilog systolic-arrays functional-coverage matrix-multiplication questasim amba-apb
Language:Verilog 8
Paebbels / pyIPCMI
A Python-based IP Core Management Infrastructure.
python3 vhdl vhdl-verification ip-core xilinx altera intel modelsim questasim riviera-pro xilinx-vivado quartus-prime synthesis simulation infrastructure database
Language:Python 8
dave2pi / SublimeLinter-contrib-vlog
SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog
modelsim questasim sublimelinter sublimelinter-plugin systemverilog verilog
Language:Python 7
yuravg / eda-scripts
Collection of scripts for EDA tools
quartus quartus-prime fpga questasim
Language:Shell 7
angrammenos97 / imc
In-Memory Accelerator Controller
controller edge-computing hdl in-memory-computing pulpissimo questasim risc-v systemverilog vivado
Language:SystemVerilog 5
edaa-org / pyEDAA.ToolSetup
eda edaa ghdl gtkwave modelsim python quartus questasim vivado
Language:Python 5
jevogel / SublimeLinter-contrib-modelsim
⚡👌 ModelSim vcom/vlog plugin for SublimeLinter. Linting for VHDL and Verilog/SystemVerilog.
linting modelsim questasim sublimelinter sublimelinter-plugin systemverilog vcom verilog vhdl vlog
Language:Python 5
Abdelrahman1810 / RTL-Verification-of-AMBA3_4-APB-Protocol
This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.
questa questasim systemverilog tcl verfication verilog degital-design
Language:SystemVerilog 4
yuravg / color_questasim
A wrapper for colorizing the output of Mentor Graphics QuestaSim messages.
modelsim perl perl5 questasim
Language:Perl 4
AhmedSobhy01 / uart-verilog
Synthesizable Verilog implementation of the classic UART 16550 serial interface implements configurable baud rate, FIFO buffering, parity, error detection, and testbenches for simulation
16550 fifo hardware-designs modelsim questasim serial-communication simulation uart uart-verilog verilog
Language:Verilog 2
AlPrime2k1 / Finite-State-Machines
Latest addition to REPO : Folder with vending machine design and TB including code coverage report
code-coverage finite-state-machine questasim testbench verilog
Language:HTML 2
dave2pi / SublimeLinter-contrib-vcom
SublimeLinter plugin for linting VHDL with Modelsim vcom
sublimelinter sublimelinter-plugin modelsim questasim vhdl
Language:Python 2
kropotin4 / SystemVerilog-examples
Попытка написать несколько примеров кода на языке SystemVerilog.
questasim systemverilog rtl
Language:SystemVerilog 2
teekamkhandelwal / SRAM_Controller
The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.
memory memory-controller questasim sram sram-controller verilog verilog-project vivado vlsi-design sram-controller-advanced sram-features-power-security-brust memory-management verlog-hdl sdram sdram-controller enhanched-sram-controller
Language:Verilog 2
teekamkhandelwal / Uart_tx_main
Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate through digital pin 0, digital pin 1.
verilog-hdl verilog-project fpga xilinx-ise questasim uart-protocol
Language:Verilog 2
aaronrjmanj / verilog
This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ arunraja08@gmail.com
hdl verilo verilog-project verilog-code modelsim questasim gvim verification
Language:Verilog 1
cad-polito-it / r4ves
RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
fault-simulation logic-simulation questasim risc-v stuck-at-faults zoix
Language:Verilog 1
flfl04 / UART_Verilog
UART 8-Bit Verilog Simple Realization
baud-rate questasim rtl
Language:Verilog 1
finjenv
NikosDelijohn / finjenv
Fault injection environment (finjenv) of permanent hardware faults for various arithmetic circuits based on QuestaSIM logic simulator
arithmetic-circuits error-modeling fault-injection questasim stuck-at-faults
Language:Verilog 1
panoskoutris / fp-multiplier
Pipelined IEEE-754 single-precision floating-point multiplier in SystemVerilog with full verification.
computer-architecture digital-design floating-point hardware-design hdl ieee-754 pipelining rtl sva system-verilog verification multiplication intel-fpga questasim simulation
Language:SystemVerilog 1
Revenant01 / Sobel_edge_detection_verilog
This project implements the Sobel edge detection algorithm in Verilog for image processing tasks. The Sobel operator is commonly used to detect edges in images by calculating the gradient magnitude at each pixel. This project explores Verilog, digital image processing, and hardware acceleration techniques for image processing.
questasim sobel-edge-detector verilog image-processing python
Language:Verilog 1
sbaldzenka / uart_core
UART IP-core for FPGA.
fpga hdl ip-core modelsim questasim uart vhdl lattice-fpga machxo3 diamond
Language:VHDL 1
SohamDas2004 / RAM-Verification-SV
Repo contains a verification environment for a custom 32RAM design using SystemVerilog
hdl systemverilog verification verilog questasim
Language:SystemVerilog 1
Hithaishisr / Router-1x3
A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.
assertions coverage digital-design fifo fsm functional-verification hardware-designs questasim rtl-design synthesis systemverilog uvm uvm-testbench vcs verilog vlsi packet-router
Language:JavaScript
jasonrodrig / ALU_SV
alu questasim systemverilog
Language:SystemVerilog
jasonrodrig / ALU_UVM
questasim systemverilog uvm alu
Language:SystemVerilog
SuggarGrandma420 / Router-1x3
🚦 Build and verify a 1x3 packet router with modular Verilog RTL and a UVM-based environment for efficient functional testing and coverage.
assertions coverage digital-design fifo fsm functional-verification hardware-designs packet-router questasim rtl-design synthesis systemverilog uvm uvm-testbench vcs verilog vlsi
Language:JavaScript

questasim

suoto / hdl_checker

Paebbels / JSON-for-VHDL

MJoergen / HyperRAM

Ghonimo / Pre_Silicon-AHB-to_APB-Verification

wyvernSemi / mem_model

NikLeberg / cosim_jtag

htminuslab / Modelsim-Unicorn

MJoergen / Avalon

Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM

Noamv7 / Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

Paebbels / pyIPCMI

dave2pi / SublimeLinter-contrib-vlog

yuravg / eda-scripts

angrammenos97 / imc

edaa-org / pyEDAA.ToolSetup

jevogel / SublimeLinter-contrib-modelsim

Abdelrahman1810 / RTL-Verification-of-AMBA3_4-APB-Protocol

yuravg / color_questasim

AhmedSobhy01 / uart-verilog

AlPrime2k1 / Finite-State-Machines

dave2pi / SublimeLinter-contrib-vcom

kropotin4 / SystemVerilog-examples

teekamkhandelwal / SRAM_Controller

teekamkhandelwal / Uart_tx_main

aaronrjmanj / verilog

cad-polito-it / r4ves

flfl04 / UART_Verilog

NikosDelijohn / finjenv

panoskoutris / fp-multiplier

Revenant01 / Sobel_edge_detection_verilog

sbaldzenka / uart_core

SohamDas2004 / RAM-Verification-SV

Hithaishisr / Router-1x3

jasonrodrig / ALU_SV

jasonrodrig / ALU_UVM

SuggarGrandma420 / Router-1x3