altera-fpga

There are 9 repositories under altera-fpga topic.

ultraembedded / openlogicbit
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
altera-fpga digital-signal-analyzer fpga ftdi2232h ftdi232h lattice-fpga logic-analyzer verilog xilinx-fpga
Language:Verilog 125
drandyhaas / HaasoscopePro
Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope
adc altera-fpga oscilloscope pyqtgraph
Language:Verilog 56
mbtaylor1982 / ReSDMAC
Verilog code to replace the Commodore SDMAC found in the A3000
altera-fpga amiga amiga-hardware intel-fpga kicad open-source quartus verilog
Language:Verilog 39
HPS2FPGAmapping
robseb / HPS2FPGAmapping
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
fpga fpga-soc intel-fpga altera altera-fpga embedded-linux can-bus fpga-fabric quartus-prime mapping-hps-peripherals bootloader soc-fpga hps fpga-configuration python-script linux intel rsyocto
Language:Verilog 36
Multimedia-Processing / Digital-Logic-Design
透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。
vhdl learn fpga altera-cyclone-v-sockit altera-cyclone-iii-de0 verilog hdl soc-kit altera-cyclone systemverilog xilinx xilinx-vivado xilinx-fpga altera-fpga altera-quartus digital-logic-design digital-logic vhdl-verilog digital verilog-hdl
Language:Verilog 15
alvarezpj / single-cycle-cpu
VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls
altera-fpga de2-board fpga quartus single-cycle vhdl
Language:VHDL 14
ThePituLegend / RISC-V_DE10-Nano
This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.
riscv risc-v riscv64 riscv-asm riscv-assembly de10-nano fpga altera altera-fpga terasic rocketchip chipyard ucberkeley
Language:Verilog 8
AccelGraph
atmughrabi / AccelGraph
Graph Processing Framework that supports || OpenMP || CAPI
accelgraph-capi graph-algorithm benchmarking-suite capi graph-framework bfs connected-components dfs triangle-counting fgpa ibm ibm-capi opencapi betweenness-centrality systemverilog pagerank altera-fpga sssp spmv accelerator
Language:SystemVerilog 7
Davide-DD / mastermind
FPGA implementation of the popular logic game using VHDL and Altera DE1
fpga fpga-game vga vga-controller vga-frame-buffer fpga-board altera altera-fpga mastermind
Language:VHDL 7
mrLSD / fpga
Research & Development FPGA projects for different boards
altera-fpga fpga sipeed-tang-nano-9k systemverilog verilog
Language:GLSL 7
rafafigueredoviana / RISCV_MCU_CYCLONEV
A basic implementation of the RISCV core into a DE10nano FPGA board.
riscv fpga altera-fpga pulpino de10nano de10-nano
Language:SystemVerilog 7
lazyoracle / vhdl-processor
An 8-bit processor in VHDL based on a simple instruction set
fpga processor-simulator vhdl digital-electronics hdl hardware-description-language hardware-designs xilinx-fpga altera-fpga verilog vivado processor processor-architecture processor-design
Language:VHDL 5
mateuspinto / FPGA_Verilog_Ballot_Box-TP2-ISL-UFV
Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.
verilog verilog-hdl verilog-project verilog-simulator fpga fpga-firmware altera-fpga altera-de2
Language:Verilog 5
HaochengBillYang / ece385
ECE385 @ UIUC FA22
systemverilog altera-fpga uiuc-ece
Language:Verilog 4
lstolcman / bachelor-thesis
Thesis covers research on digital signal processing with software defined radio techniques applied in FPGA environment. It is written entirely in Polish language, except english abstract
fpga altera-fpga verilog signal-processing sdr dcf77 dcf-decoder hardware digital-signal-processing digital-design altera
Language:Verilog 4
MUDAL / Altera_FPGA_Projects
This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.
altera-fpga electronics embedded-systems fpga modelsim quartus-prime rtl-design-and-verification stm32 vhdl
Language:C 4
Terminatorjjjjj / NTUEE-DCLAB-Materials
This repo is the lab materials for NTUEE DCLAB (http://dclab.ee.ntu.edu.tw).
altera-fpga
Language:SystemVerilog 4
XAli-SHX / Implementation-of-an-Edge-Detection-Filter-Using-the-Avalon-Interface
Implementation of an Edge Detection Filter Using the Avalon Interface
altera-fpga avalon avalon-bus edge-detection fpga rgb2gray verilog avalon-streaming sobel sobel-edge-detector sobel-filter quartus
Language:Verilog 4
arnaldojr / Robot-FPGA
Controle de motor DC + Sensores fim de curso implementado em VHDL para o kit DE0-CV utilizado na matéria de Elementos de sistemas do 3 semestre de Engenharia da computação do Insper.
de0 de0cv de0-cv fpga vhd altera altera-fpga insper engenharia-de-computacao robo robot-fpga robo-fpga l298n l298n-h-bridge l298
Language:VHDL 3
mohamedtareq24 / 4_Channel_Logic_Analyzer
FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA
altera-fpga fpga logic-analyzer quartus-prime verilog
Language:Verilog 3
nikolovjovan / FPGAParallelSorting
Altera Quartus project for Altera Cyclone III FPGA boards which uses one manager board and two worker boards to sort an array of numbers in parallel.
altera altera-fpga cyclone-iii terasic-de0 vhdl
Language:VHDL 3
samdejong86 / Arria-V-ADC-Ethernet
Transfers data from an ADC to a PC via ethernet
arria-v quartus altera-fpga nios2 socket telnet adc ethernet verilog vhdl
Language:Verilog 3
william-hazem / LASD
Laboratório de Arquitetura de Sistemas Digitais, ministrado pelo professor Rafael Bezerra Correia Lima. Foram desenvolvidos 8 requisitos de hardware, 1 requisito de software e 1 projeto de disciplina que totalizam 10 Sprints. A arquitetura de sistemas implementada é baseada em MIPS 8 bits, e desenvolvidos e testados na FGPA Ciclone II EP2C35F672C6
altera-fpga mips verilog
Language:Verilog 3
asankaSovis / Position_Detection
📌 The idea of this project is to build a system that uses the existing lights to detect the location of a user within an indoor environment. For this, we can use Visible Light Communication (VLC) technology. The basic concept is to have four LEDs transmitting their IDs one after the other at fixed intervals.
altera-fpga arduino c-sharp fpga intel serial-communication uart-protocol visible-light-communication
Language:Verilog 2
chkrr00k / sram-controller
A simple sram controller and test for the altera DE1 FPGA board
vhdl vhdl-modules vhdl-coursework sram sram-controller vhdl-sram altera-fpga altera-de1 terasic-de1
Language:VHDL 2
EngineerMichael / ModelSim-Altera-Project-Electronics-
⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.
altera-de1 altera-fpga altera-quartus modelsim synchronous-counter vhdl-code
2
iancraz / EV21-Processor
Verilog RISC Processor Design
processor processor-architecture risc quartus-prime cyclone-iv altera altera-fpga cyclone cyclone-v hdl pipeline verilog verilog-code verilog-hdl verilog-project
Language:Verilog 2
t4rcisio / Arquivos_Verilog
Processador nano-Risc, controlaor de display, e muito mais...
fpga verilog vhdl intel altera-fpga quartus
Language:Verilog 2
yvan674 / Hardware-Praktikum
Hardware Praktikum at Uni Freiburg
robotics fpga arduino-pro-mini quartus-prime altera-fpga cyclone-iv custom-pcb
Language:VHDL 2
Chrisdeleon91 / Altera-DE1-VGA-Interface
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
altera-de1 altera-fpga intel quartus-prime vhdl vhdl-coursework finite-state-machine fsm quartus2 vga-controller vga-driver
Language:VHDL 1
gaikwadabhishek / flappy-bird-fpga-vhdl
Flappy Bird on FPGA using VHDL
altera-fpga cyclone-ii flappy-bird fpga fpga-programming vhdl
Language:HTML 1
JavierAGalvis / Pong-FPGA
Pong VGA for a DE0 Altera model FPGA programmed in VHDL.
vhdl-code vhdl-examples vhdl-elearning altera-fpga pong-game vga-controller
Language:VHDL 1
MatheusAndrade1 / Digital-Clock-in-VHDL
Digital clock in VHDL, on Altera Cyclone IV FPGA Board A-C4E6. This work was presented on PLP discipline during electrical engineer course at Mackenzie Presbyterian University.
vhdl vhdl-code digital-solutions altera-fpga
Language:VHDL 1
MinhTran0911 / DS1302_Interface_DE10
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
altera-fpga cyclone-v ds1302 hardware-description-language hdl modelsim quartus-prime rtc-module systemverilog terasic-de10-standard
Language:SystemVerilog 1
MinhTran0911 / UART_DE10
UART Receiver and Transmitter using Terasic DE-10 Standard FPGA
altera-fpga hardware-description-language hdl modelsim quartus-prime systemverilog terasic-de10-standard uart
Language:SystemVerilog 1
MKme / fpga
FPGA and CPLD programming, tutorials and information I figure out.
fpga altera-fpga altera cpld verilog
Language:VHDL 1

altera-fpga

ultraembedded / openlogicbit

drandyhaas / HaasoscopePro

mbtaylor1982 / ReSDMAC

robseb / HPS2FPGAmapping

Multimedia-Processing / Digital-Logic-Design

alvarezpj / single-cycle-cpu

ThePituLegend / RISC-V_DE10-Nano

atmughrabi / AccelGraph

Davide-DD / mastermind

mrLSD / fpga

rafafigueredoviana / RISCV_MCU_CYCLONEV

lazyoracle / vhdl-processor

mateuspinto / FPGA_Verilog_Ballot_Box-TP2-ISL-UFV

HaochengBillYang / ece385

lstolcman / bachelor-thesis

MUDAL / Altera_FPGA_Projects

Terminatorjjjjj / NTUEE-DCLAB-Materials

XAli-SHX / Implementation-of-an-Edge-Detection-Filter-Using-the-Avalon-Interface

arnaldojr / Robot-FPGA

mohamedtareq24 / 4_Channel_Logic_Analyzer

nikolovjovan / FPGAParallelSorting

samdejong86 / Arria-V-ADC-Ethernet

william-hazem / LASD

asankaSovis / Position_Detection

chkrr00k / sram-controller

EngineerMichael / ModelSim-Altera-Project-Electronics-

iancraz / EV21-Processor

t4rcisio / Arquivos_Verilog

yvan674 / Hardware-Praktikum

Chrisdeleon91 / Altera-DE1-VGA-Interface

gaikwadabhishek / flappy-bird-fpga-vhdl

JavierAGalvis / Pong-FPGA

MatheusAndrade1 / Digital-Clock-in-VHDL

MinhTran0911 / DS1302_Interface_DE10

MinhTran0911 / UART_DE10

MKme / fpga