quartus-prime

There are 3 repositories under quartus-prime topic.

CTSRD-CHERI / quartus-install
Install Intel FPGA 'Quartus Prime' software on remote servers
quartus quartus-prime fpga
Language:Python 48
RomeoMe5 / DDLM
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
ddlm verilog labs terasic-de10-lite terasic hse miem schoolmips mips mips-architecture verilog-designs fsm alu quartus modelsim dmk-press verilog-book system-verilog tcl quartus-prime
Language:Verilog 48
HPS2FPGAmapping
robseb / HPS2FPGAmapping
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
fpga fpga-soc intel-fpga altera altera-fpga embedded-linux can-bus fpga-fabric quartus-prime mapping-hps-peripherals bootloader soc-fpga hps fpga-configuration python-script linux intel rsyocto
Language:Verilog 34
arthurmteodoro / install-quartus-linux
Tutorial de instalação do Quartus Prime no Linux
quartus-linux quartus-prime fpga fpga-linux modelsim install-script
Language:Shell 33
fpga-defender
w3arycod3r / fpga-defender
A recreation of Williams Defender 1981 arcade game for DE10-Lite FPGA dev board, written in VHDL.
fpga defender vhdl de10-lite quartus-prime
Language:VHDL 28
MinatsuT / CYC1000_SDRAM
A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)
fpga cyclone-10lp cyc1000 sdram quartus-prime sdram-controller nios2
Language:Verilog 12
egk696 / EDAC_SDRAM_Controller
Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
fpga fault-tolerant sdram vhdl quartus-prime vivado sdram-controller cots-sdram embedded-systems
Language:Verilog 9
Jefferson-Lopes / quartus-installation
Full tutorial about how to install Quartus Prime software in different systems
installation quartus-linux quartus-prime ubuntu
9
Nathen-Smith / FPGA-super-mario-bros
FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1
systemverilog nios2 quartus-prime fpga-soc
Language:Verilog 9
Paebbels / pyIPCMI
A Python-based IP Core Management Infrastructure.
python3 vhdl vhdl-verification ip-core xilinx altera intel modelsim questasim riviera-pro xilinx-vivado quartus-prime synthesis simulation infrastructure database
Language:Python 8
osafune / peridot_peripherals
PERIDOT Standard peripherals
peridot platform-designer qsys quartus-prime
Language:C 7
socfpgaPlatformGenerator
robseb / socfpgaPlatformGenerator
Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs
soc-fpgas quartus-prime soc-eds sd-card-image linux-distribution u-boot build-automation intel-fpga cyclone-v arria10
Language:Python 7
addisonElliott / LogiFindFPGATest
This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.
altera quartus-prime logifind fpga verilog verilog-hdl uart-verilog nec-verilog ir-receiver cyclone-iv 7-segment buzzer ep4ce6e22c8n pl2303 easyfpga
Language:Verilog 6
jagumiel / irReceiver
Remote control infrared signal receiver programmed in VHDL for a Terasic DE1-SoC board.
vhdl vhdl-code ir-receiver quartus-prime ir-decoder infrared-decoder
Language:VHDL 6
pa-tiq / vending_machine
fpga de10-lite de10nano de10-nano quartus-prime quartus quartus-18-1 verilog verilog-project
Language:Verilog 6
pandyah5 / ECE241_Verilog
This repo contains all the Verilog HDL files that I made during the course.
verilog verilog-hdl logisim quartus-prime
Language:Verilog 6
yuravg / eda-scripts
Collection of scripts for EDA tools
quartus quartus-prime fpga questasim
Language:Shell 6
samdejong86 / Cyclone-V-ADC-UART
Sends data from an ADC to a UART-USB interface
quartus-prime fpga uart daq verilog signaltap cyclone-v cyclone-v-gx-starter-kit data-conversion-card serial pyserial finite-impulse-response
Language:VHDL 5
arnav-gudibande / fpga-intro-guide
Introductory guide to building and programming FPGAs
fpga fpga-development hdl modelsim quartus quartus-prime
Language:Tcl 4
MinatsuT / VidorGdev
Game development library for MKR VIDOR 4000
arduino-fpga cyclone-10lp fpga mkrvidor4000 quartus-prime verilog
Language:C 4
JorgeAskur / Tic-Tac-Toe-FPGA
A recreation of the popular game Tic-Tac-Toe for the DE10-Lite FPGA dev board, in VHDL.
vhld de10-lite quartus-prime tic-tac-toe
Language:VHDL 3
meetdoshi90 / 8-Bit-RISC-Microprocessor
An 8-bit RISC based processor designed in verilog with x86 instructions.
verilog risc-processor x86 8-bit cpu quartus-prime modelsim fpga microprocessor 8-bit-computer
3
ngiambla / qvmi
Quick Verilog Module Isolator - Isolates a design for testing.
cpp11 dut fpga hdl high-level-synthesis intel-quartus isolated-modules isolator quartus-prime regex verilog verilog-hdl vivado vivado-hls xilinx-fpga
Language:Verilog 3
prithvi-narayan-bhat / Custom_RISC_Implementation
An attempt at making a customised RISC processor with five pipelined stages and supporting all RISC-V instruction set
arm assembly hdl intel linux quartus-prime risc-v riscv riscv32 systemverilog-hdl verilog verilog-hdl
Language:SystemVerilog 3
riscygeek / quartus-make
This is a template for projects using the Quartus Prime suite with the DE10-Lite FPGA board.
de10-lite quartus quartus-prime makefile makefile-template template template-project
Language:Verilog 3
RomeoMe5 / SystemGenerator-FPGA-Marsohod.org-schoolMIPS
CAD for automatically configuring FPGA "Marsohod"
verilog quartus quartus-prime miem hse python system-generator system-verilog fpga
Language:Verilog 3
SamanKhamesian / Special-Purpose-Processor
This project is an implementation of a special-purpose processor that can calculate greatest common multiple (GCM) and least common factor (LCM) for two inputs based on input operation code (Opcode)
vhdl quartus-prime processor state-machine fpga de2-115 lcm gcm controller
Language:Verilog 3
tharinduSamare / Multicore_processor_verilog_design
This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.
fpga simulation verilog quartus-prime modelsim
Language:Verilog 3
yuravg / quartus_cadence_netlist_merger
Quartus pin and Cadence Allegro net-list merger
cadence python quartus quartus-prime
Language:Python 3
yuravg / system_console
Tcl packages for Quartus Prime System Console(FPGA debugging).
fpga quartus quartus-prime system-console
Language:Tcl 3
aliaagheisX / AES
AES implementation using verilog
aes aes-128 aes-256 aes-cipher aes-encryption fpga modelsim quartus quartus-prime verilog
Language:Verilog 2
cmruderman / HW-SW-Compression-Decompression
HW/SW compression and decompression of captured image
altera arm fpga qsys quartus-prime soc
Language:Verilog 2
FaresAtef1 / AES-Advanced-Encryption-Standard
256-bit Advanced Encryption Standard Implemented with Verilog HDL.
aes-128 aes-256 aes-encryption hardware-description-language aes-de quartus-prime fpga
Language:Verilog 2
iancraz / EV21-Processor
EV21 RISC Processor Design
processor processor-architecture risc quartus-prime cyclone-iv altera altera-fpga cyclone cyclone-v hdl pipeline verilog verilog-code verilog-hdl verilog-project
Language:Verilog 2
reda-i / digital_timer
A Quartus prime project that implements a 0 to 99 counter on 7 segment display using Altera DE10-Lite board
verilog quartus-prime
Language:Verilog 2
ywassef / HydraProcessor
C- minus compiler for the Hydra microprocessor architecture
verilog verilog-project quartus-prime fpga-board fpga altera
Language:Verilog 2

quartus-prime

CTSRD-CHERI / quartus-install

RomeoMe5 / DDLM

robseb / HPS2FPGAmapping

arthurmteodoro / install-quartus-linux

w3arycod3r / fpga-defender

MinatsuT / CYC1000_SDRAM

egk696 / EDAC_SDRAM_Controller

Jefferson-Lopes / quartus-installation

Nathen-Smith / FPGA-super-mario-bros

Paebbels / pyIPCMI

osafune / peridot_peripherals

robseb / socfpgaPlatformGenerator

addisonElliott / LogiFindFPGATest

jagumiel / irReceiver

pa-tiq / vending_machine

pandyah5 / ECE241_Verilog

yuravg / eda-scripts

samdejong86 / Cyclone-V-ADC-UART

arnav-gudibande / fpga-intro-guide

MinatsuT / VidorGdev

JorgeAskur / Tic-Tac-Toe-FPGA

meetdoshi90 / 8-Bit-RISC-Microprocessor

ngiambla / qvmi

prithvi-narayan-bhat / Custom_RISC_Implementation

riscygeek / quartus-make

RomeoMe5 / SystemGenerator-FPGA-Marsohod.org-schoolMIPS

SamanKhamesian / Special-Purpose-Processor

tharinduSamare / Multicore_processor_verilog_design

yuravg / quartus_cadence_netlist_merger

yuravg / system_console

aliaagheisX / AES

cmruderman / HW-SW-Compression-Decompression

FaresAtef1 / AES-Advanced-Encryption-Standard

iancraz / EV21-Processor

reda-i / digital_timer

ywassef / HydraProcessor