digital-system-design

There are 1 repository under digital-system-design topic.

ekb0412 / 100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
digital-system-design asic fpga xilinx-vivado verilog-hdl vlsi-design
Language:Verilog 101
hadis98 / IUT
All my projects, homework, hand writings, course slides and anything I have learned and done during my studies at IUT😊. feel free to give it a ⭐=)
algorithms architecutre automata-theory compiler-design computer-networks database-lab data-structures microprocessor network-lab operating-systems signals-and-systems advanced-programming basic-programming codevision digital-system-design proteus
Language:Jupyter Notebook 36
Fahad-Habib / RISC-V-Single-Cycle-Processor
Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA
digital-system-design risc-v single-cycle-processor systemverilog verilog risc-v-architecture
Language:SystemVerilog 21
kimianoorbakhsh / Verilog-Matrix-Multiplier
Final Project for Digital Systems Design Course, Fall 2020
digital-system-design modelsim verilog xilinx
Language:Verilog 14
Amey-Thakur / DIGITAL-LOGIC-DESIGN-AND-ANALYSIS-AND-DIGITAL-SYSTEM-LAB
CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>
computer-science engineering computer-engineering digital-logic-design digital-logic-design-lab digital-systems digital-system-design digital-systems-design textbooks ameythakur amey megasatish
10
samiyaalizaidi / Equalizer
Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications
digital-signal-processing digital-system-design fir-filters audio-equalizer audio-processing digital-signal-processing-filters digital-systems-design equalizer filter-design fpga verilog verilog-hdl xilinx-vivado
Language:Verilog 10
samiyaalizaidi / FIR-Filter
Implementation of a low-pass FIR filter in Verilog HDL.
digital-signal-processing digital-system-design digital-systems-design fir-filters low-pass-filters matlab verilog-hdl
Language:Verilog 9
EnAnsari / digital-system
My activity in digital systems
digital-system-design digital-systems matlab proteus simulink
4
marcelcases / bachelor-thesis
Implementation and verification of a hardware-based controller for a three-phase induction motor on an FPGA — Bachelor's Thesis [UPC-TTU, 2019]
fpga vhdl digital-system-design
Language:VHDL 4
Amirreza81 / Digital-Systems-Design
Digital Systems Design - Spring 2023 - Sharif University of Technology
assembly digital-system-design verilog
Language:Verilog 3
Fahad-Habib / RISC-V-Pipelined-Processor-with-CSR
3-stage RISC-V Pipelined Processor with interrupt CSR support
risc-v risc-v-architecture risc-v-assembly digital-system-design systemverilog
Language:SystemVerilog 3
samiyaalizaidi / Direct-Digital-Synthesizer
Direct Digital Synthesizer for Generating Sine Waves using Verilog HDL
direct-digital-synthesizer sine-wave-generator verilog-code verilog-hdl digital-system-design
Language:Verilog 3
ATOMIC09 / CalculatorVHDL
Binary Adder, Subtractor, Multiplier, Divider in VHDL with FPGA board.
calculator digital-system-design fpga vhdl
Language:VHDL 2
bori00 / ATM
Digital System Design Course (1st year, 2nd Semester)
automata digital-system-design finite-state-machine fpga
Language:VHDL 2
chinmay1724 / NITK-IT
This GitHub repository Consists of materials, code samples, documentation, and valuable resources related to the Information Technology (IT) Department at the National Institute of Technology Karnataka (NITK). 📚 Resource Library 💻 Code Samples 🗂️ Project Repositories
assignment automata code compiler-design computer-networks data-structures-and-algorithms database-management design-and-analysis-of-algorithms digital-system-design discrete-mathematics object-oriented-programming opearting-system papers probability-and-statistics projects questions quiz signals-and-systems web-technologies
Language:Jupyter Notebook 2
KyloReneo / FIFO_BUFFER
FIFO Buffer Implemented in VHDL
buffer digital-system-design fifo-buffer vhdl fifo-controller
Language:VHDL 2
pjbk / Logic-Circuit-Design-Lab-Work-
Digital Logic Design (DLD) is a fundamental subject for the engineering students worldwide. Well, many students find it difficult to design the digital circuits properly while pursuing the DLD course in colleges or universities. Therefore, I will try to assist those students by sharing my lab works with them.
digital-logic-design logic-circuit-design dld-lab-manual digital-system-design
2
samiyaalizaidi / FIFO-In-Verilog
Implementation of a FIFO structure for Digital Systems | Written in Verilog HDL
digital-system-design fifo-buffer fifo-queue verilog-hdl vivado
Language:Verilog 2
samiyaalizaidi / FPGA
Verilog implementation of the basic structure of an FPGA
digital-system-design fpga verilog vivado
Language:Verilog 2
sidhantp1906 / Adcanced_Digital_Logic_Design-01fe19bec187
Lab projects using Verilog HDL
digital-system-design spartan-3 verilog xilinx xilinx-fpga
Language:Verilog 2
YosafatM / ESCOM_Arquitectura_de_Computadoras
Repositorio con las 12 prácticas en VHDL para el curso impartido por la profesora Nayeli Vega, tomada en la ESCOM, IPN.
digital-system-design vhdl mips
Language:VHDL 2
ahnafshahrear / Signal-Processing-EEG
Academic Lab Course of the 27th batch of Computer Science & Engineering | University of Rajshahi - 🇧🇩
verilog digital-system-design
Language:Verilog 1
AsierCL / Logisim-PC
Very basic computer created in Logisim Evolution. Just to show off your computer architecture skills.
basic-computer computer-architecture digital-system-design logisim-evolution
1
Fahad-Habib / UART-Tx
UART Tx implemented in SystemVerilog from scratch.
digital-system-design uart uart-verilog
Language:SystemVerilog 1
gorkemkose / CS303_Project_Labs
Term project and lab assignments for CS303 - Logic and Digital System course in Sabancı University, Fall 2021-2022.
sabanci-university cs303 digital-system-design
Language:JavaScript 1
hgrover19 / ECE241_Home_Simulation_Final_Project
Home automation simulation project created for the UofT ECE241 course. Worked on by Harsh Grover and Joonseo Park. More details in README
digital-system-design verilog
Language:Verilog 1
marcelcases / digital-systems-design-with-vhdl-labs
Digital Systems Design With VHDL laboratory sessions, Fall 2018
fpga vhdl digital-system-design
Language:VHDL 1
melchisedech333 / verilog-experiments
:space_invader: My studies with Verilog and notions of digital systems.
digital-system-design digital-systems digital-systems-design digital-systems-fundamentals hdl icarus-verilog verilog verilog-code verilog-examples verilog-hdl verilog-project
Language:Verilog 1
Samuelbec025 / Verilog-Matrix-Multiplier
This is a simple project that shows how to multiply two 8x8 matrixes in Verilog.
digital-system-design matrix matrix-multiplication verilog xilinx xilinx-vivado
Language:Verilog 1
shantanu-pande / Traffic-Lights-Controller
Digital Hardware Description for four way crossing
digital-system-design traffic-light-controller vhdl
Language:VHDL 1
sidhantp1906 / AMBA4-APB
Advanced Pheripheral Bus design using verilog HDL
amba-apb amba4 digital-system-design protocols rtl-design verilog
Language:Verilog 1
sidhantp1906 / Resume
Contains my resume
digital-system-design resume resume-template verilog vlsi-design
1
T-Deekshitha / RTL-Design-of-16-bit-ALU
The ALU is a crucial component of digital systems, responsible for executing arithmetic and logical operations. This project is an RTL design of 16 bit ALU using verilog.
digital-system-design verilog
1
tothantonio / UTCN
personal files for courses I took at Technical University of Cluj-Napoca
assembly c vhdl analysis algebra-linear data-structures-and-algorithms digital-system-design java database oop computer-architecture operating-system
Language:C++ 1
wasifijaz / Digital-System-Design-Verilog-Implementation
Digital System Design Verilog Implementation
digital-system-design verilog verilog-code verilog-simulator lifo fifo logic-gates adders subtractor
Language:Verilog 1
KyloReneo / NoC
A Comprehensive VHDL implementation of a Network-on-Chip router architecture and interconnections.
arbiter digital-system-design ip-core network-interface network-on-chip noc router vhdl
Language:VHDL

digital-system-design

ekb0412 / 100DaysofRTL

hadis98 / IUT

Fahad-Habib / RISC-V-Single-Cycle-Processor

kimianoorbakhsh / Verilog-Matrix-Multiplier

Amey-Thakur / DIGITAL-LOGIC-DESIGN-AND-ANALYSIS-AND-DIGITAL-SYSTEM-LAB

samiyaalizaidi / Equalizer

samiyaalizaidi / FIR-Filter

EnAnsari / digital-system

marcelcases / bachelor-thesis

Amirreza81 / Digital-Systems-Design

Fahad-Habib / RISC-V-Pipelined-Processor-with-CSR

samiyaalizaidi / Direct-Digital-Synthesizer

ATOMIC09 / CalculatorVHDL

bori00 / ATM

chinmay1724 / NITK-IT

KyloReneo / FIFO_BUFFER

pjbk / Logic-Circuit-Design-Lab-Work-

samiyaalizaidi / FIFO-In-Verilog

samiyaalizaidi / FPGA

sidhantp1906 / Adcanced_Digital_Logic_Design-01fe19bec187

YosafatM / ESCOM_Arquitectura_de_Computadoras

ahnafshahrear / Signal-Processing-EEG

AsierCL / Logisim-PC

Fahad-Habib / UART-Tx

gorkemkose / CS303_Project_Labs

hgrover19 / ECE241_Home_Simulation_Final_Project

marcelcases / digital-systems-design-with-vhdl-labs

melchisedech333 / verilog-experiments

Samuelbec025 / Verilog-Matrix-Multiplier

shantanu-pande / Traffic-Lights-Controller

sidhantp1906 / AMBA4-APB

sidhantp1906 / Resume

T-Deekshitha / RTL-Design-of-16-bit-ALU

tothantonio / UTCN

wasifijaz / Digital-System-Design-Verilog-Implementation

KyloReneo / NoC