There are 1 repository under mips-architecture topic.
5-stage pipelined 32-bit MIPS microprocessor in Verilog
It's all coming back into focus!
A computer system containing CPU, OS and Compiler under MIPS architecture.
5 stage pipelined MIPS-32 processor
:heavy_check_mark: Examples to learn Mips
A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall
Linux kernel source tree with the latest features and modifications to unleash the full potential of Ingenic processors.
Some of my assembly code (examples, iterative and recursive algorithms) from Computer's Architecture course in Sapienza University, CS Bachelor's Degree :floppy_disk:
A snake game developed in assembly for MIPS processor
Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.
MIPS architecture implemented in Verilog.
A Simple 5-stage 32-bit pipelined processor with Harvard architecture and a RISC-like instruction set architecture.
Bubble Sort in MIPS
This is a MIPS 5 stage 32-bit pipelined processor with Harvard architecture, which comes with an assembler to interpret instructions to supported OP codes.
MIPS programs with MARS system calls
Assignment from the Advanced Computer Architecture class.
Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.
Cheatsheet completinha do MIPS 32 bits - MIPS Technologies
An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler
CSE-306-Computer-Architecture Offline / Assignment on ALU, Floating Point Adder and 8 bit MIPS Datapath along with pipelining
An Assembler to read and parse MIPS Assembly code and then generate an output file
DEPRECATED!!! An (almost) fully functional theme engine for MARS.
My attempt at reverse engineering my modem's firmware
Dmitry Grinberg's uMIPS emulator on the Raspberry Pi Pico
A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
Qt 5 package for OpenWRT
A 32-bit MIPS processor developed in Verilog based on pipeline
A simple MIPS processor implemented using Verilog capable of supporting basic I,J and R type instructions. Built using Xilinx Vivado 2019.1
An implementation of 32-bits MIPS Single Cycle Datapath in Verilog HDL.
Lasalle University - Computer Architecture 2020/1 - Assembly + MIPS architecture
Processador MICO X1 implementado no Digital.