axi-lite

There are 0 repository under axi-lite topic.

hdl-modules
hdl-modules / hdl-modules
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
altera amd asic axi axi-lite cdc clock-domain-crossing eda efinix fpga hardware intel ip microsemi rtl vhdl vivado xilinx asynchronous-fifo fifo
Language:VHDL 82
hdl-registers
hdl-registers / hdl-registers
An open-source HDL register code generator fast enough to run in real time.
asic axi eda fpga rtl axi-lite register register-interface csr generator html python vhdl c cplusplus
Language:Python 25
rooinasuit / AXI_to_SPI
Designing means to communicate as an SPI master, being a part of AXI interface
fpga verilog axi-lite functional-verification spi systemverilog uvm
Language:Verilog 11
chclau / axi_lite_reg-
Registers bank with Axi-Lite interface
axi-lite vhdl vhdl-code vhdl-examples
Language:VHDL 3
MasterPlayer / adxl345-sv
FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
fpga systemverilog zynq adxl345 i2c axi-stream axi-lite interrupts
Language:C 3
aryan-programmer / axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
artix artix-7 basys3 fpga vitis vivado xilinx xilinx-fpga axi axi-lite axi-memory-mapped axi-stream embedded hls vitis-hls vivado-ip-integrator vivado-vitis xilinx-hls xilinx-vitis xilinx-vivado
Language:TeX 2
aryan-programmer / axi_stream_array_sum_microblaze
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
artix artix-7 axi axi-lite axi-stream basys3 embedded fpga hls vitis vitis-hls vivado vivado-ip-integrator vivado-vitis xilinx xilinx-fpga xilinx-hls xilinx-vitis xilinx-vivado microblaze
Language:C 1
Bucknalla / axis-interfacer
Extract AXI (Full, Lite and Stream) interfaces from Verilog source files
axi axi-lite axis verilog xilinx
1
farukyld / sort-circuit
an RTL circuit that sorts the integer values in a momory unit connected with (almost) AXI-Lite
axi-lite insertion-sort rtl-design state-machine verilog
Language:Verilog 0
riyasach189 / PYNQ-Examples
This is a collection of some examples designed in the Vivado Design Suite.
amd axi-lite axi-stream hls jupyter pynq pynq-z2 rfsoc4x2 vivado xilinx
Language:Tcl
suoglu / AXI-lite-slave
Slaves for AXI-lite interface
arty axi-lite basys3 fpga gpio nexys-video
Language:Tcl

axi-lite

hdl-modules / hdl-modules

hdl-registers / hdl-registers

rooinasuit / AXI_to_SPI

chclau / axi_lite_reg-

MasterPlayer / adxl345-sv

aryan-programmer / axi_gen_and_sum_primes_fpga

aryan-programmer / axi_stream_array_sum_microblaze

Bucknalla / axis-interfacer

farukyld / sort-circuit

riyasach189 / PYNQ-Examples

suoglu / AXI-lite-slave