Michael Jørgensen (MJoergen)

MJoergen

User data from Github https://github.com/MJoergen

Company:Weibel Scientific

Location:Denmark

Home Page:http://www.linkedin.com/in/michaeljoergensen

GitHub:@MJoergen

Michael Jørgensen's repositories

nexys4ddr

Various projects for the Nexys4DDR board from Digilent

HyperRAM

Portable HyperRAM controller

Language:VHDLLicense:MITStargazers:51Issues:7Issues:7

C64MEGA65

Commodore 64 core for the MEGA65 based on the MiSTer FPGA C64 core

Language:VHDLLicense:GPL-3.0Stargazers:32Issues:13Issues:163

65c02

Implementation of the 65C02 CPU suitable for FPGA.

Language:AssemblyLicense:MITStargazers:16Issues:6Issues:0

Avalon

Utilities for Avalon Memory Map

Language:VHDLLicense:MITStargazers:9Issues:5Issues:1

SDCard

Portable SDCard controller

Language:VHDLLicense:MITStargazers:3Issues:3Issues:0

SDRAM

SDRAM controller

Language:VHDLLicense:MITStargazers:3Issues:1Issues:0

VIC20MEGA65

VIC 20 for the MEGA65 based on the MiSTer core

Language:VHDLLicense:GPL-3.0Stargazers:3Issues:6Issues:1
Language:VerilogStargazers:1Issues:2Issues:0

math

Various mathematical doodling

Language:TeXStargazers:1Issues:3Issues:0

MEGA65

Various projects for the MEGA65 platform

Language:VHDLLicense:MITStargazers:1Issues:1Issues:0

ac701

Test designs for the AC701 evaluation board

Language:VerilogLicense:MITStargazers:0Issues:0Issues:0

bit_dump

Dump Xilinx FPGA bitfiles

Language:PythonStargazers:0Issues:0Issues:0

C64_MiSTerMEGA65

Git submodule of the Commodore 64 core for the MEGA65

Language:SystemVerilogStargazers:0Issues:2Issues:0

EDID-for-HDMI

EDID for HDMI products using I2C

Language:VHDLStargazers:0Issues:0Issues:0
Language:VHDLLicense:MITStargazers:0Issues:2Issues:0

krebs

Krebs cycle

Language:TeXLicense:MITStargazers:0Issues:2Issues:0

m65dbg

An enhanced remote serial debugger/monitor for the mega65 project

Language:CLicense:GPL-3.0Stargazers:0Issues:0Issues:0

mega65-core

MEGA65 FPGA core

Language:VHDLLicense:NOASSERTIONStargazers:0Issues:1Issues:0

MEGA65-cores

A collection of alternative cores for the MEGA65 based on the M2M framework

Language:VHDLLicense:GPL-3.0Stargazers:0Issues:1Issues:2

MEGA65-life

Conway's Game of Life on the MEGA65 using the MiSTer2MEGA65 framework

Language:VHDLLicense:GPL-3.0Stargazers:0Issues:0Issues:0

MiSTeX-boards

Core generation scripts for various FPGA boards

Language:VerilogLicense:BSD-3-ClauseStargazers:0Issues:1Issues:0

musik

Akkorder til sange

License:MITStargazers:0Issues:0Issues:0

sdspi

SD-Card controller, using a SPI interface that is (optionally) shared

Language:VerilogStargazers:0Issues:1Issues:0

steiner

Calculates Steiner Systems

Language:VHDLLicense:MITStargazers:0Issues:2Issues:1

UART-for-Tang-Primer-20K

A UART translated from Verilog to VHDL for the Tang Primer 20K

Language:VHDLStargazers:0Issues:0Issues:0

VIC20_MiSTer

Commodore VIC-20 for MiSTer

Language:VHDLStargazers:0Issues:1Issues:0

xapp884

PRBS Generator & Checker

Language:VHDLStargazers:0Issues:0Issues:0

zxuno4mega65

ZX-Uno port for MEGA65 delivering a fully fledged ZX Spectrum 48k and 128k

Language:VHDLLicense:GPL-3.0Stargazers:0Issues:1Issues:0

zybo20

Playground for my Zybo Z7-20 board from Digilent

License:MITStargazers:0Issues:0Issues:0