verilog-designs

There are 3 repositories under verilog-designs topic.

RomeoMe5 / DDLM
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
ddlm verilog labs terasic-de10-lite terasic hse miem schoolmips mips mips-architecture verilog-designs fsm alu quartus modelsim dmk-press verilog-book system-verilog tcl quartus-prime
Language:Verilog 48
varkenvarken / fpga-experiments
Some verilog designs for an icestick40
verilog verilog-project ice40 icestick icebreaker verilog-designs fpga hardware cpu icestorm
Language:Verilog 3
Nimit3-droid / Automatic-abstract-model-computation-from-Verilog-design-descriptions
Modeling hardware systems involves abstracting away wide datapaths but keeping low-level details of the underlying control logic in place. Consequently, the state space is significantly reduced and intricate control interactions can be formalized. The abstraction process in these languages, however, must be done manually, an error-prone task.
abstraction automatic verilog-designs hacktoberfest2022 hactoberfest hactoberfest-accepted open-source hactoberfest-2022 hactoberfest-2022-accepted hactoberfest-approved hactoberfest2022
Language:Verilog 2

RomeoMe5 / DDLM