There are 4 repositories under xilinx-vivado topic.
Repurposing existing HDL tools to help writing better code
Xilinx Virtual Cable Server for Raspberry Pi
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
**科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
This repository contains all labs done as a part of the Embedded Logic and Design course.
SPI ELF bootloader for Xilinx Microblaze processors
Extremely basic CortexM0 SoC based on ARM DesignStart Eval
Bazel rules for Xilinx Vivado
Repository to store all design and testbench files for Senior Design
The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga display. Picoblaze processor is used to control the Analog & Digital displays of the clock.
A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
2d Images processing system with FPGA (Zynq 7k) from two dragster linescanner (DR-2k-7)
A Xilinx IP Core and App for line scanner image capture and store
透過數位邏輯結合VHDL與Verilog的過程,作為從基礎數位邏輯到計算機系統結構,並實作出一顆CPU的教學書籍,希望未來可以成為教學範例檔案。目前將開發轉移到GitLab,因為可以呈現數學與MUL圖。
FPGA Cryptography for High-Level Synthesis
SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2
Real-Time Operating System (RTOS) for Xilinx Zynq-7000 Cortex-A9 (ARMv7-A) multi-core SoCs (ZedBoard, PicoZed, MicroZed and similars) based on the ARINC 653 Part 1 specification
Framework for emulation of non volatile memory using off-the-shelf FPGAs
EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
FPGA Reliability Evaluation through JTAG
A single cycle MIPS RISC-V CPU Core using Verilog
Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs
This project aims to design a hardware encryption and decryption scheme for the Data Encryption Standard (DES) algorithm