xilinx-vivado

There are 4 repositories under xilinx-vivado topic.

ZipCPU / wb2axip
Bus bridges and other odds and ends
axi-bus fpga gplv3 wishbone wishbone-bus xilinx xilinx-vivado
Language:Verilog 439
suoto / hdl_checker
Repurposing existing HDL tools to help writing better code
vhdl modelsim xilinx verilog systemverilog python hdl xilinx-vivado syntax-checker lsp-server vivado-simulator ghdl vim hdl-checker language-server coc-nvim questasim mentor-msim vim-ale emacs-lsp
Language:Python 184
derekmulcahy / xvcpi
Xilinx Virtual Cable Server for Raspberry Pi
jtag snickerdoodle xilinx-fpga xilinx-vivado zynq
Language:C 103
nxbyte / Verilog-Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
adder comparator decoder encoder full-adder half-adder look-ahead-adder multiplexer priority ripple-adder simulator system-verilog testbenches traffic-light-controller verilog xilinx xilinx-vivado
Language:Verilog 99
ultraembedded / usb2sniffer
USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
usb-scanning usb-debugging usb usb2 fpga xilinx-vivado rtl verilog usb-analyzer usb-sniffer artix-7 lambdaconcept-usb2sniffer-hardware wireshark
Language:Verilog 47
pontazaricardo / Verilog_Calculator_Matrix_Multiplication
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
verilog vhdl calculator matrix-multiplication xilinx xilinx-ise xilinx-vivado xilinx-fpga low-level-programming hardware-designs ic-design
Language:Verilog 43
Domipheus / ArtyS7-RPU-SoC
Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
fpga fpga-soc firmware c vhdl vivado xilinx-vivado risc-v riscv riscv32 hdmi dvid spi apache2
Language:VHDL 36
sailordiary / computer-systems-ucas
**科学院大学计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
verilog cpu xilinx-vivado xilinx-fpga computer-systems
Language:Verilog 29
ekb0412 / 100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
digital-system-design asic fpga xilinx-vivado verilog-hdl vlsi-design
Language:Verilog 28
sarthak268 / Embedded_Logic_and_Design
This repository contains all labs done as a part of the Embedded Logic and Design course.
verilog verilog-hdl verilog-programs verilog-project embedded-systems embedded-logic logic-circuit logic-programming embedded-c c vhdl vhdl-code zedboard xilinx xilinx-vivado xilinx-fpga xilinx-sdk arm vivado pmod
22
hdlguy / make_for_vivado
experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
tcl xilinx-vivado gnu-make fpga
Language:Tcl 21
henrikbrixandersen / elf-bootloader
SPI ELF bootloader for Xilinx Microblaze processors
bootloader elf spi vivado xilinx xilinx-sdk xilinx-vivado
Language:C 20
siorpaes / BareBonesCortexM0
Extremely basic CortexM0 SoC based on ARM DesignStart Eval
mcu cortex-m0 fpga rtl verilog soc hardware-designs xilinx-vivado vivado
Language:Verilog 20
agoessling / rules_vivado
Bazel rules for Xilinx Vivado
rules-vivado xilinx-vivado bazel bitstream vivado xilinx fpga verilog bazel-rules
Language:Python 18
Wissance / QuickSPI
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
spi-hdl spi axi spi-ip-core spi-pld spi-fpga spi-interface verilog-spi axi-interfaces bit-oriented-spi soft-spi hard-spi dragster-spi fpga xilinx-fpga xilinx-vivado altera verilog-snippets verilog-hdl verilog-components
Language:Verilog 18
senior_design_puf
Crimsonninja / senior_design_puf
Repository to store all design and testbench files for Senior Design
testbenches systemverilog verilog physical-unclonable-functions ring-oscillator rtl hardware-security hardware-designs xilinx-vivado
Language:Verilog 17
muhammadaldacher / FPGA-Design-of-a-Digital-Analog-Clock-Display-using-Digilent-Basys3-Artix-7
The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga display. Picoblaze processor is used to control the Analog & Digital displays of the clock.
fpga digital-design picoblaze-processor xilinx-vivado verilog vhdl assembly-language
Language:VHDL 13
shinde-shantanu / FPGA_TDC
Time to Digital Converter on an FPGA
verilog fpga xilinx-vivado nexys4ddr
Language:VHDL 12
splAcharya / DigitalOscilloscope_Zynq7000Soc
A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.
zedboard digital-oscilloscope xilinx-fpga xilinx-vivado zynq-7000 fpga-soc verilog-hdl embedded-systems
12
Yourigh / Rotary-encoder-VHDL-design
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
axi encoder rotary vivado xilinx-fpga xilinx-vivado zybo zynq zynq-7010
Language:VHDL 12
Wissance / 2DImageProcessing
2d Images processing system with FPGA (Zynq 7k) from two dragster linescanner (DR-2k-7)
dr-2k-7 2d image-processing frequency-analysis optical-measurements dragster awaiba cmosis 2d-scaner frequency-measurment optics optical optical-system optical-sensors fpga verilog optical-mark-recognition xilinx-fpga xilinx-vivado computer-vision
Language:VHDL 11
Wissance / ImageCaptureSystem
A Xilinx IP Core and App for line scanner image capture and store
dragster linescanners image video capture-the-flag cmosis awaiba two-channel-image-capture-system axi-vdma axi-quad-spi video-ip-core dr-2k-7 spi scanner xilinx-ip xilinx-fpga xilinx-vivado xilinx-axi-vdma computer-vision
Language:VHDL 11
Multimedia-Processing / Digital-Logic-Design
透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。
vhdl learn fpga altera-cyclone-v-sockit altera-cyclone-iii-de0 verilog hdl soc-kit altera-cyclone systemverilog xilinx xilinx-vivado xilinx-fpga altera-fpga altera-quartus digital-logic-design digital-logic vhdl-verilog digital verilog-hdl
Language:Verilog 10
petrsocha / hls-crypto
FPGA Cryptography for High-Level Synthesis
cryptography encryption fpga fpga-soc high-level-synthesis digital-design digital side-channel side-channel-attacks side-channel-safe vivado vivado-hls xilinx xilinx-fpga xilinx-vivado security hardware-security hardware hardware-designs hardware-cryptography
Language:C++ 10
kuoyaoming93 / sem-ip_pynq
SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2
soft-error xilinx xilinx-vivado xilinx-fpga zynq pynq pynq-hardware-overlay pynq-z1 pynq-z2 python uart axi icap jupyter-notebook sem-ip
Language:Tcl 9
SimpleSoC
siorpaes / SimpleSoC
Very simple Cortex-M1 SoC design based on ARM DesignStart
soc arm cortex-m xilinx-fpga xilinx-vivado designstart digitaldesign systemonchip fpga-soc fpga cortex-m1 hardware-designs verilog mcu
Language:C 9
lfarcaro / ARINC653_ARMV7A_Z7000
Real-Time Operating System (RTOS) for Xilinx Zynq-7000 Cortex-A9 (ARMv7-A) multi-core SoCs (ZedBoard, PicoZed, MicroZed and similars) based on the ARINC 653 Part 1 specification
arm cortex cortex-a cortex-a9 xilinx xilinx-vivado zynq zynq-7000 zynq-7010 zynq-7020 arinc arinc653 z7-lite
Language:C 8
Paebbels / pyIPCMI
A Python-based IP Core Management Infrastructure.
altera database infrastructure intel ip-core modelsim python3 quartus-prime questasim riviera-pro simulation synthesis vhdl vhdl-verification xilinx xilinx-vivado
Language:Python 8
simoneruffini / NORM
Framework for emulation of non volatile memory using off-the-shelf FPGAs
vhdl fpga xilinx-fpga xilinx-vivado non-volatile-memory feram openhardware
Language:VHDL 8
matthiaskonrath / rc4-verilog
EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.
cpp fpga-accelerator opencl python rc4 verilog xilinx-hls xilinx-vivado
Language:C++ 7
Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC
neeraj1397 / Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
prefix-adder adder prefix-tree kogge-stone-adder brent-kung han-carlson ladner-fischer verilog vivado xilinx-fpga xilinx-vivado zynq-7000 fpga ripple-carry-adder carry-look-ahead-adder carry-save-adder
Language:Verilog 7
unipieslab / FREtZ
FPGA Reliability Evaluation through JTAG
fault-injection fault-tolerance fpga python reliability tcl xilinx-vivado
Language:Tcl 7
ad-astra-et-ultra / RISC-V-CPU-Core
A single cycle MIPS RISC-V CPU Core using Verilog
computer-architecture cpu microprocessor risc-v xilinx-vivado verilog
Language:Verilog 6
lastweek / fpga_vivado_resources
A set of Vivado dev resources.
vivado tcl fpga microblaze partial-reconfiguration xilinx xilinx-vivado lastweek-source
6
luminoso / cr-countones
Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs
finite-state-machine fpga nexys4ddr vivado xilinx xilinx-fpga xilinx-vivado
Language:VHDL 6
164adityakumar / Image_Encryption_I-CHIP
This project aims to design a hardware encryption and decryption scheme for the Data Encryption Standard (DES) algorithm
encryption-decryption fpga verilog verilog-hdl verilog-project cryptography encoding image image-processing cipher opencv data-encryption data-encryption-standard rtldesign source-coding vivado xilinx xilinx-vivado
Language:Verilog 5

xilinx-vivado

ZipCPU / wb2axip

suoto / hdl_checker

derekmulcahy / xvcpi

nxbyte / Verilog-Projects

ultraembedded / usb2sniffer

pontazaricardo / Verilog_Calculator_Matrix_Multiplication

Domipheus / ArtyS7-RPU-SoC

sailordiary / computer-systems-ucas

ekb0412 / 100DaysofRTL

sarthak268 / Embedded_Logic_and_Design

hdlguy / make_for_vivado

henrikbrixandersen / elf-bootloader

siorpaes / BareBonesCortexM0

agoessling / rules_vivado

Wissance / QuickSPI

Crimsonninja / senior_design_puf

muhammadaldacher / FPGA-Design-of-a-Digital-Analog-Clock-Display-using-Digilent-Basys3-Artix-7

shinde-shantanu / FPGA_TDC

splAcharya / DigitalOscilloscope_Zynq7000Soc

Yourigh / Rotary-encoder-VHDL-design

Wissance / 2DImageProcessing

Wissance / ImageCaptureSystem

Multimedia-Processing / Digital-Logic-Design

petrsocha / hls-crypto

kuoyaoming93 / sem-ip_pynq

siorpaes / SimpleSoC

lfarcaro / ARINC653_ARMV7A_Z7000

Paebbels / pyIPCMI

simoneruffini / NORM

matthiaskonrath / rc4-verilog

neeraj1397 / Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC

unipieslab / FREtZ

ad-astra-et-ultra / RISC-V-CPU-Core

lastweek / fpga_vivado_resources

luminoso / cr-countones

164adityakumar / Image_Encryption_I-CHIP