verilog-project

There are 82 repositories under verilog-project topic.

• sudhamshu091 / 32-Verilog-Mini-Projects

  Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

  miniprojectverilogverilog-hdlverilog-project
  Language:Verilog 513

• Gowtham1729 / Image-Processing

  Image Processing Toolbox in Verilog using Basys3 FPGA

  verilogverilog-hdlverilog-projectvhdlpython3basys3basys-boardbasysfpgapixelconvolutionhsyncbasys3-fpgamotion-blurrampythoncoevivadoimage-processingdigital-systems
  Language:VHDL 172

• zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

  Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

  simdprocessorverilogprocessor-designverilog-projectmultiplieradderinstruction-set-architecturecadence-virtuosocpualu
  Language:Verilog 113

• neelkshah / MIPS-Processor

  5-stage pipelined 32-bit MIPS microprocessor in Verilog

  computer-architecturecomputer-organizationcomputer-organisationmicroprocessormicroprocessorsbits-pilaniverilogverilog-hdlverilog-projectverilog-programsverilog-componentsverilog-snippetsverilog-simulatormips-processormips-architecturemips-instructions
  Language:Verilog 110

• snbk001 / Verilog-Design-Examples

  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

  verilogtestbenchesverilog-designverilog-codeverilog-hdlverilog-programsverilog-projectself-checking
  Language:Verilog 72

• adibis / DDR2_Controller

  DDR2 memory controller written in Verilog

  verilogverilog-projectddrhdl
  Language:Verilog 68

• michaelehab / AES-Verilog

  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

  aesaes-128aes-192aes-256aes-decryptionaes-encryptioncryptographyfpgafpga-boardfpga-socrtlverilogverilog-hdlverilog-projectencryptionencryption-decryptionsecuritylearn
  Language:Verilog 63

• ashishrana160796 / verilog-starter-tutorials

  Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

  hdlverilogcircuitswitchesiverilogverilog-hdlup-for-grabsbeginner-friendlylogic-gatespracticeverilog-programsverilog-snippetsverilog-projectembedded-systems
  Language:Verilog 51

• mongrelgem / Verilog-Adders

  Implementing Different Adder Structures in Verilog

  adderverilogverilog-projectverilog-hdlhardware-designs
  Language:Verilog 50

• xiazhuo / nscc2022_personal

  NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）

  mips32nscscc2022-singleverilog-project
  Language:VHDL 47

• TheSUPERCD / 8bit_MicroComputer_Verilog

  This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

  verilogverilog-hdlverilog-projectverilog-codeiverilog8bitben-eaterben-eaters-cpu
  Language:Verilog 46

• prajwalgekkouga / AHB-to-APB-Bridge

  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

  ahbambaapbdigitalfpgamodelsimverilogverilog-project
  Language:Verilog 44

• Arjun-Narula / Traffic-Light-Controller-using-Verilog

  the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

  verilogverilog-hdlverilog-projectverilog-codeverilog-programsverilog-simulatorvivadovivado-hlsvivado-simulatortraffictraffic-lighttraffic-sign-recognition
  Language:JavaScript 36

• vedic-partap / Computer-Organization-and-Architecture-LAB

  Solution to COA LAB Assgn, IIT Kharagpur

  coahardware-designsverilog-projectverilogcpumips-assembly
  Language:Verilog 35

• mihir8181 / VerilogHDL-Codes

  Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

  verilogverilog-projectverilog-codeverilog-programsverilog-hdln-bit-alucounterfsmmoore-machine-codemealy-machine-codeverilogvalidationtestbenchesdesign-under-testfifoasynchronousasynchronous-fifofifo-bufferfifo-verilog
  Language:Verilog 34

• sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog

  Single Cycle RISC MIPS Processor

  verilogrisc-processorverilog-projectrisc-vrisc
  Language:Verilog 28

• Akashtailor-exe / 30-days-of-verilog

  30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

  30-days-of-code30daysofcodedigital-logic-designdigitalcircuitverilogverilog-projectvlsirtl-codingrtl-designverilog-programs
  27

• adibis / Interrupt_Controller

  An 8 input interrupt controller written in Verilog.

  verilogverilog-projectverilog-componentshdl
  Language:Verilog 24

• ultraembedded / minispartan6-audio

  miniSpartan6+ (Spartan6) FPGA based MP3 Player

  mp3playerfpgarisc-vspartan6verilogverilog-projectaudiosd-cardrv32im
  Language:Verilog 24

• sarthak268 / Embedded_Logic_and_Design

  This repository contains all labs done as a part of the Embedded Logic and Design course.

  verilogverilog-hdlverilog-programsverilog-projectembedded-systemsembedded-logiclogic-circuitlogic-programmingembedded-ccvhdlvhdl-codezedboardxilinxxilinx-vivadoxilinx-fpgaxilinx-sdkarmvivadopmod
  23

• coole198669 / viterbi_decoder

  Hardware Viterbi Decoder in verilog

  verilog-projectviterbi-decoder
  Language:Verilog 20

• pendkeomkar / SPI

  Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.

  veriloguvmverilog-hdlverilog-programsverilog-projectverificationverification-methodologiesverification-codesverification-componentspi
  16

• RPG-7 / HGA101_GPU

  gpgpusoc-suiteverilog-project
  Language:Verilog 16

• tongplw / Undertale-Verilog

  👻 Simple Undertale-like game on Basys3 FPGA written in Verilog

  undertalebasys3basys3-fpgaverilogverilog-projectfpgafpga-gamefpga-boardvgauart
  Language:Verilog 16

• lorentsinani / 16bitCPU-Verilog

  16 bit CPU created in Vivado with Verilog

  computer-architectureverilogverilog-project
  Language:Verilog 15

• mnmhdanas / DA-Based-LMS-Adaptive-filter

  Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .

  digital-designlms-algorithmadaptive-filterfir-filterverilog-projectverilogdistributed-arithmetic
  Language:Verilog 13

• sudhamshu091 / RISC-Pipelined-Processor-32-bit-Verilog

  Simple Pipelined 32 bit RISC Processor

  pipeline-riscrisc-vriscverilogverilog-projectverilog-processor
  Language:Verilog 13

• sudhamshu091 / Single-Cycle-Risc-Pipelined-Processor-Verilog

  Single Cycle MIPS Pipelined Processor using Verilog

  verilogrisc-processorpipelined-riscriscverilog-project
  Language:Verilog 13

• flasonil / Serial-Multiplier

  16 bit serial multiplier in SystemVerilog

  verilogverilog-projectsystemverilogsystem-verilog
  Language:SystemVerilog 12

• NikhilMukraj / spiking-neural-networks-hardware

  An FPGA design for simulating biological neurons

  biological-neuronscomputational-biologyfpga-acceleratorizhikevich-neuronsneural-networksystemverilog-hdlverilog-project
  Language:SystemVerilog 12

• aekanshd / booths-multiplier-using-verilog

  verilogverilog-projectbooths-algorithm
  Language:Verilog 11

• powerplayer9 / Voice-Based-Motor-Control

  A verilog HDL based project to control a servomotor with voice commands from an android phone.

  verilog-projectverilog-hdlservo-motorquartusde10-nanobluetoothterasic-rfsmotor-controllervoice-commands
  Language:Verilog 11

• emrealci / FPGA-Verilog

  Practices related to the fundamental level of the programming language Verilog.

  comparatorfpgafrequency-dividerhardware-designshdllatchmultiplexersr-latchverilogverilog-componentsverilog-projectxilinx-fpga
  Language:Verilog 10
• my_rtl_code

  Nidhinchandran47 / my_rtl_code

  Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

  hdlrtl-codingverilogverilog-hdlverilog-programsverilog-projectvlsifpgasystem-verilogvhdl
  Language:Verilog 10

• vasanthkumar18 / Cache-Compression

  Cache compression using BASE-DELTA-IMMEDIATE process in verilog

  cachecache-compressionbdi-modelprojectverilog-projectverilog-codehardware-projecthacktoberfesthacktoberfest2021
  Language:Verilog 10

• cw1997 / SDRAM-Controller

  SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

  sdramsdram-controllerverilog-projectsystemveriloghardwarehardware-designs
  Language:HTML 9