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tianrenz2 / Single-Cycle-Processor

Single-Cycle RISC-V Processor in systemverylog

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systemverilogmodelsimverification

Single-Cycle-Processor

Single-Cycle RISC-V Processor in systemverylog

Developed and Tested on ModelSim

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Single-Cycle RISC-V Processor in systemverylog

systemverilogmodelsimverification

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Language:SystemVerilog 70.5%Language:Tcl 17.9%Language:Stata 8.7%Language:Shell 2.9%