There are 1 repository under ripple-carry-adder topic.
All the projects and assignments done as part of VLSI course.
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
work done as part of VLSI Design practice course
Parametrized Verilog implementation of different architectures of adder / subtractor circuits.
Digital System Design Lab Codes using Verilog
An 4-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.
A repository for some modules I made while learning Verilog
Progetto di Elettronica Digitale AA 2022-2023
My VHDL Codes during EE214 (Digital Lab) Spring 2020-21
Computer Architecture - Practical Solution with Quartus - Sharif University of Technology
porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation
Skript zur Einführung in die Digitaltechnik
A 4-bit ripple-carry adder-subtractor created in Logisim.
Useful VHDL scripts for hardware description.
designed simple digital circuits using verilog