Hi👋, I'm Ekansh Bansal, and I'm currently immersing myself in the world of VLSI🎯, focusing on RTL design using Verilog HDL. My goal is to learn RTL within 1️⃣0️⃣0️⃣ days, and I rely on Xilinx Vivado 2022.2 Design Suite🚀 for synthesizing and simulating RTL codes👨🏼💻. This powerful tool💪🏼 allows me to efficiently develop complex digital circuits, including FPGAs and ASICs. I'm excited about my journey and the potential it holds for equipping me with valuable skills that I can apply to real-world problems in the future.
Here is the list of Day wise RTL Codes:-
Day: 1-> Behavioral Modeling Style