xilinx-vitis

There are 0 repository under xilinx-vitis topic.

triSYCL / sycl
SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
xilinx-fpga xilinx-vitis trisycl oneapi-dpc sycl-compilation accelerators clang llvm dpc-toolchain cpp20 sycl
107
nodamushi / vivado_cmake_module
CMake for Xilinx Vivado/Vitis
cmake xilinx-vivado xilinx-vitis xilinx-hls
Language:CMake 5
aryan-programmer / axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
artix artix-7 basys3 fpga vitis vivado xilinx xilinx-fpga axi axi-lite axi-memory-mapped axi-stream embedded hls vitis-hls vivado-ip-integrator vivado-vitis xilinx-hls xilinx-vitis xilinx-vivado
Language:TeX 2
aryan-programmer / axi_stream_array_sum_microblaze
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
artix artix-7 axi axi-lite axi-stream basys3 embedded fpga hls vitis vitis-hls vivado vivado-ip-integrator vivado-vitis xilinx xilinx-fpga xilinx-hls xilinx-vitis xilinx-vivado microblaze
Language:C 1
ArioKian / Xilinx_Zynq7000_ZynqUltraScalePlus_PS_SdCardDrivers
Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.
zynq-7000 zynq-7020 zynq-example-project zynq-ultrascale xilinx xilinx-fpga xilinx-sdk xilinx-vitis xilinx-vivado xilinx-zynq zynq zynq-7010
Language:C 0
efetunca / Zynq-7000-TFTP-Server
A TFTP server running on Zynq-7000
tftp tftp-server vitis xilinx xilinx-sdk xilinx-vitis xilinx-zynq zynq zynq-7000
Language:C 0
dennisleexyz / vitis-2019.2
:bookmark: Downgrade to 2019.2
arch arch-linux archlinux aur aur-packages fpga fpga-programming vitis vivado vivado-installer vivado-vitis xilinx xilinx-fpga xilinx-vitis xilinx-vivado
Language:Shell
justin-marian / cla-16bits-adder
Carry-Lookahead 16-bits Adder (CLA16) computes sums by rapidly determining carry bits through parallel processing.
carry-look-ahead-adder cpp xilinx-vitis 16bits 4bits
Language:C++