There are 2 repositories under xilinx-ise topic.
An example of how to use the Xilinx ISE toolchain from the command line
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)
This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools
FPGA Tetris written in Verilog
The Repository contains the code of various Digital Circuits
A Verilog based Fractal Set Generator for the Xilinx Artix 7
Tiny 4-bit CPU using AMD2901 bit slice (https://github.com/Amrnasr/AM2901) and program memory initialized from a file
Xilinx Virtual Cable (XVC) Server implementation for use with an Arduino UNO/Leonardo
An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.
A single cycle CPU running MIPS instructions on Xilinx FPGA
Simple Ping Pong game on Xilinx Spartan 3E
Simple system built around VHDL implementation of Am9080 8-bit CPU based on 29XX bit-slice series of devices, as described here: https://en.wikichip.org/w/images/7/76/An_Emulation_of_the_Am9080A.pdf
ALINX-AX309-RTC-UART-VHDL-FPGA-Xilinx-Spartan6
RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.
16-bit MIPS processor implemented in Verilog (as a part of Computer Organisation course)
16 Bit Scientific Calculator Using Xilinx ISE 14.7 on Xilinx ISE, EDA Playground and Simple 4 bit calculator on Spartan 6 Board
A multiple cycle CPU running MIPS instructions on Xilinx FPGA
This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.
This rep contains neighbour's cpu. Single-cycle/Multi-cycle CPU implementation in vhdl using ISE Xiling for the course 'Computer Organization' at TUC
A VHDL implementation of a MIPS processor with multicycle instruction fetching
Introductory Verilog project for Digilent CoolRunner-II Starter Board featuring Xilinx XC2C256-7-TQ144 CPLD
FPGA Messbauer hardware (generator, emulation of signal from gamma-source registered and amplified
Microgramming technology applied to my multiple cycle CPU
Soft Error Vulnerability Analysis Framework for Xilinx FPGAs
To implement the elevator controller, we used Verilog as HDL. The focus of our project was the implementation and verification of a controller for a basic elevator functionality. We also proposed a methodology that utilizes the SCAN algorithm to enhance the efficiency and reliability of the controller.
Design and implement a Seven Segment Display available on the BASYS3 board (FPGA) in VHDL
Design of the implementation of a calculator connected on the integrated FPGA
A repository for Digital System Design Laboratory, providing labs and a project covering digital circuits, CAD tools, VHDL, FPGA, and ICs.
Hardware Schematic of Four Bit Signed Calculator designed using Xilinx ISE 14.7
This is a basic project of Arithmetic Logic Unit that takes two input of 8 Bits each and undergoes 8 different operations and generates an output of 16 Bits
Small project to track things with a waterproof sonar sensor
This repository contains the source codes for design of circuits written in VHDL using Xilinx (14.7), which were practiced as a part of my CA lab during my BTech 4th semester.