Ekansh Bansal's repositories
100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
1-bit_6T_SRAM
This repository contains the analysis and simulation of 6T SRAM using Cadence Virtuoso EDA on different technology nodes (45nm, 90nm, 180nm) and some leakage reduction technique.
MPL-2.0000
UART-Serial-Port-Module-Design-Main-ASIC-
This repository contains a project on a VLSI Front-End design (UART) using Verilog HDL
Language:Verilog000