Muhammad Aldacher's repositories
Analog-Design-of-Asynchronous-SAR-ADC
This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.
Layout-Design-of-an-8x8-SRAM-array
The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Noise Margin is obtained through Matlab scripts.
Analog-Design-of-1.9-GHz-PLL-system
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp
This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.
RF-design-of-1.9-GHz-Rx-frontend
This project shows the design process of the main blocks of a typical RX frontend system.
Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC
This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
FPGA-Design-of-a-Digital-Analog-Clock-Display-using-Digilent-Basys3-Artix-7
The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga display. Picoblaze processor is used to control the Analog & Digital displays of the clock.
Analog-design-of-4-bit-current-steering-DACs
This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using high-swing cascode current mirror structures for the current source arrays.
Analog-Design-of-Bootstrapped-Switch
This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A comparison is done between several topologies, showing the ENOB, SNR, & SFDR achieved in each case.
Analog-Design-of-Dynamic-Comparator
This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Power / (fs*2ENOB).
Modeling-of-4-bit-Flash-ADC-and-4-bit-DAC
This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
RF-design-of-2.4-GHz-LNA
This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.
Layout-Design-for-an-8-bit-Microprocessor
Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS VLSI technology on Tanner EDA toolchain.
Signal-Processing-DTFT-and-Convolution
This project is about designing generalized MATLAB codes that perform discrete convolution and discrete-time Fourier transform (DTFT) to audio and voice signals. Signal-processing MATLAB functions like “conv”, “filter”, and “fir1” are used to manipulate the input voice signal with different filters and study the output spectrum.
Signal-Processing-Z-Transform-and-Tone-Reduction
This project is about using a simple Z-transform transfer function of a digital filter that filters out certain noise frequencies in an input signal using MATLAB.
Analog-Design-of-LDO-with-PMOS-pass-device
This project discusses the design procedure of a Low Dropout Voltage Regulator (LDO) circuit.