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Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
explore different implementations of adders and study their characteristics.
Different adders code in VHDL and Comparison
Summary of projects I did in VLSI desing.
Computer Architecture - Practical Solution with Quartus - Sharif University of Technology
Useful VHDL scripts for hardware description.