There are 4 repositories under zynq-7000 topic.
Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
Firmware with overclock support for LibreSDR (PlutoSDR clone with Zynq 7020), 27.5 MSPS sample rate over Gigabit Ethernet with libiio/PlutoSDR API
FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD
Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)
⚙️ 基于 Zynq-7 全可编程 SoC 的设计
KVM over IP Gateway targeting Zynq-7000 SoC
This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
Global Dark Mode for ALL apps on ANY platforms.
This is xc7z020clg400 FPGA hardware core board design
A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.
Dual-Mode PSK Transceiver on SDR With FPGA
POSIX-compatible tiny multi-threading library for Intel Nios II / Xilinx Zynq-7000
SpaceVNX (VITA 74.4) carrier based on Zynq-7000.
AD9361 FM Radio Verilog LVDS
Hardware and Software Co-design implementations
Implementation of a VGA Controller in Verilog (Both Graphics Mode and Text Mode)
Real-Time Operating System (RTOS) for Xilinx Zynq-7000 Cortex-A9 (ARMv7-A) multi-core SoCs (ZedBoard, PicoZed, MicroZed and similars) based on the ARINC 653 Part 1 specification
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
This repository documents Interfacing HDMI and VGA with Pynq Z2 Board using Vivado block design and RTL.
This repository contains the C code for ARM Implementation of FFT on Zynq-7000 APSoC from Xilinx.
Simple tutorials for getting started with programming on Trenz ArduZynq boards.
This repository contains my Linux builds and projects for ZYBO Zynq dev board
A ZYNQ 7020 project that plays breakout via HDMI.
Simple safe lock mechanism written in SystemVerilog.
MSc Final Project
FPGA design automation for real-time, dynamic partially reconfigurable application
Yocto layer for the FRED framework
Deep Learning Processing Unit (DPU IP) integration with Application Processing Unit (APU) using (Zynq-7000 PS) in Xilinx Vivado Design Suite
A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)