adder

There are 0 repository under adder topic.

Telegram-Members-Adder
saifalisew1508 / Telegram-Members-Adder
Telegram Members Adding Software/Script Using Termux.
members-adder members-adding-script python telegram telegram-channel telegram-group-member-adder telegram-group-member-scraper telegram-group-scraper termux tele-members adder adder-telegram python-script scraper telethon termux-hacking termux-tool members-script scraper-tools telegram-member-adder
Language:Python 561
AbirHasan2005 / TelegramScraper
Using this tool you can easily add so many members from any group to your group. Less than 2 minutes. Super easy. Time saver. But this tool is only for educational purpose. You could be banned from Telegram. So be careful. Recommanded to use this tool only on Termux.
telegram-group saver termux scraper telegram-scraper-bot telegram-scraper telegram-bots smsbot adder
Language:Python 502
DenizShabani / telegramscraper
Scraper and adder for Telegram supporting multiple accounts at the same time. Adds via Telegram API and only by username. For adding via ID and not needing Telgram API contact me.
adder osint programming python scraper script telegram
Language:Python 355
zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
simd processor verilog processor-design verilog-project multiplier adder instruction-set-architecture cadence-virtuoso cpu alu
Language:Verilog 111
antonblanchard / vlsiffra
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
amaranth-hdl booth dadda physical-design verilog vlsi adder multiplier
Language:Python 103
nxbyte / Verilog-Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
verilog xilinx half-adder full-adder ripple-adder look-ahead-adder comparator decoder encoder multiplexer traffic-light-controller xilinx-vivado adder testbenches simulator priority system-verilog
Language:Verilog 98
Psingh12354 / HackerRank-Certification
HackerRank Certification Question
hackerrank-solutions test python python3 hackerrank-certification java solution problem-solving code python-shape gaming laptop reverse average string anagram adder class shape sql
Language:Python 93
suoglu / Fixed-Floating-Point-Adder-Multiplier
16-bit Adder Multiplier hardware on Digilent Basys 3
fpga vivado verilog hardware adder multiplier fixed-point floating-point binary16
Language:Verilog 58
mongrelgem / Verilog-Adders
Implementing Different Adder Structures in Verilog
adder verilog verilog-project verilog-hdl hardware-designs
Language:Verilog 50
IamFlea / AdderCircuitGenerator
This script generates and analyzes prefix tree adders.
adder digitalcircuit koggestone sklansky ladnerfischer brentkung hancarlson knowles han-carlson prefix-tree brent-kung kogge-stone-adder sklansky-adder adders-generator ladner-fischer digital-circuit paralel-adder prefix-graph delay fanout
Language:Python 37
evilbream / TG_adder_with_proxy
Telegram Group Parser/Scraper and user Adder via id or username with proxy support
adder proxy telegram-adder telegram-adding-tool telegram-scraper scraper session
Language:Python 31
sumukhathrey / Verilog_ASIC_Design
Verilog for ASIC Design
hardware hardware-modelling verilog sequence-detector testbench rtl counter adder gates
Language:Verilog 22
RaulMurillo / Flo-Posit
Posit Arithmetic Cores generated with FloPoCo
posit unum vhdl flopoco posit-arithmetic adder multiplier
Language:VHDL 20
Damantha126 / TelegramScraper
Using this tool you can easily add so many members from any group to your group. Less than 2 minutes. Super easy. Time saver. But this tool is only for educational purpose. You could be banned from Telegram. So be careful. Recommanded to use this tool only on Termux.
adder and scraper telegram
Language:Python 14
mattvenn / instrumented_adder
Instrumenting adders to measure speed
adder asic hardware ngspice simulation sky130
Language:Verilog 12
BlackFoxTM / Tadder
Adds members of another group to another group
adder python telegram telegram-group
Language:Python 11
KiranThomasCherian / VLSI-and-Computer-Architecture
Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim
verilog iverilog kogge-stone-adder carry-propogate-adders gate-layout xilinx vlsi cmos-path-enumerator wallace-tree-multiplier sklansky-adder magic-tool pipeline pipelined computer-architecture floating-point floating-point-arithmetic adder hardware-modules
Language:Verilog 11
seahore / turing-machine-emulator
一个命令行的图灵机演示模拟器
turing-machine turing-machine-simulator whu adder cpp11 introduction-to-computer-science educational-project
Language:C++ 8
svelte-compose / svelte-compose
⚠️ MOVED: https://github.com/svelte-add/svelte-add/ ⚠️ Add different tools to your new or existing svelte / svelte-kit project
adder bootstrap bulma composer kit mdsvex svelte svelte-add svelte-kit tailwindcss svelte-compose
Language:TypeScript 8
hosseinfani / digital_odyssey
Materials for the Computer Science course, Digital Design (Logic Circuits)
digital-design logic-circuits digital-systems number-systems boolean-algebra logic-gates canonical-forms karnaugh-map combinational-logic adder subtractor multiplexer sequential-logic flip-flop registers shift-register counter memory programmable-logic decoding
Language:C++ 7
KamelAbdelouahab / CNN-Resource-Model
Models to estimate the hardware cost of FPGA based implementations of CNNs
fpga cnn caffe linear-models adder
Language:Python 7
Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC
neeraj1397 / Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
prefix-adder adder prefix-tree kogge-stone-adder brent-kung han-carlson ladner-fischer verilog vivado xilinx-fpga xilinx-vivado zynq-7000 fpga ripple-carry-adder carry-look-ahead-adder carry-save-adder
Language:Verilog 7
vincent-camus / carry-cut-back-adder
Carry Cut-Back Adder (CCBA) - An approximate adder circuit with artificially-built false timing paths
approximate-computing adder low-power timing-optimization
Language:VHDL 6
Unimool / TelegramAdder
adder telegram scraper telegram-api telegram-bot telegram-group telegramadder scrape telegrammembers telegramadd telegramscrape telegram-adder telegram-member telegram-scraper telegrambot telegramscraper telegram-tool telegramtool telegram-member-adder telegram-member-scraper
Language:Python 5
domainoverflow / diy-domaining-challenge
DIY Domaining Challenge Custom Domain Marketplace
domaining landing-page css-grid domains cpanel diy custom-domain marketplace monetization digital-assets diy-domaining-challenge bulk lander adder xml-api pos nginx apache website-template css-grid-layout
Language:PHP 4
tirtharajsinha / vhdl_codes
vhdl
vhdl vhdl-code logic-gates logic-gate-simulator universal-gate adder subtractor circuit-design truth-table diagram
Language:VHDL 4
adityagupta1089 / EEP206-Verilog
Verilog Codes for various digital circuits for labs at IIT Ropar, basic gates, adders & subtractors (half & full), ripple adders, multipliers and code converters.
adder subtractor digital-circuits ripple-adders gates multipliers verilog bcd
Language:Verilog 3
ed-ke / 50-002_2D_Challenge_2018
Design challenge for the 50.002 module for the fastest 2-SAT solver and the best performance-area ratio for a 32-bit adder.
java adder satisfiability papadimitriou jsim design sutd mit han-carlson 32-bit istd
Language:Java 3
neelabhro / Complex-Adder-with-SSD
Complex Adder with Seven Segment Display
fpga basys3 fsm finite-state-machine seven-segments-display adder
Language:Verilog 3
Parrot043 / android_device_lenovo_a5000_adder_oreo
Lenovo A5000 (adder) - mt6582 - device tree
lenovo a5000 adder oreo device binder
Language:C 3
Parrot043 / android_vendor_lenovo_a5000_adder_oreo
Lenovo A5000 (adder) - mt6582 - vendor files
lenovo a5000 adder oreo binder vendor patch
Language:Makefile 3
PXVI / std_module
All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.
verilog-modules verilog-code rtl shifter siso adder subtractor fifo mux encoder decoder lfsr
Language:Verilog 3
sujoyyyy / Computer-Architecture
In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems.
adder floating-point single-precision-floating-point verilog
Language:Verilog 3
minecraftdixit / Digital-ASIC-LAB
Verilog Codes for various Design
adder fifo max-pooling pipeline sequence-detector system-verilog uvm verilog one-detector reconfigurable-matrix-adder multiplication verilog-hdl
Language:SystemVerilog 2
Telegram-Member-Adder
mosmduali / Telegram-Member-Adder
Python Member Adder For Telegram
adder api engineering github python python3 pythonapi telegram-bot telegram-bot-api
Language:Python 2
muznahsaqiib / 3-bit-adder-
3-bit adder dld source-code verilog verilog-hdl
2

adder

saifalisew1508 / Telegram-Members-Adder

AbirHasan2005 / TelegramScraper

DenizShabani / telegramscraper

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

antonblanchard / vlsiffra

nxbyte / Verilog-Projects

Psingh12354 / HackerRank-Certification

suoglu / Fixed-Floating-Point-Adder-Multiplier

mongrelgem / Verilog-Adders

IamFlea / AdderCircuitGenerator

evilbream / TG_adder_with_proxy

sumukhathrey / Verilog_ASIC_Design

RaulMurillo / Flo-Posit

Damantha126 / TelegramScraper

mattvenn / instrumented_adder

BlackFoxTM / Tadder

KiranThomasCherian / VLSI-and-Computer-Architecture

seahore / turing-machine-emulator

svelte-compose / svelte-compose

hosseinfani / digital_odyssey

KamelAbdelouahab / CNN-Resource-Model

neeraj1397 / Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC

vincent-camus / carry-cut-back-adder

Unimool / TelegramAdder

domainoverflow / diy-domaining-challenge

tirtharajsinha / vhdl_codes

adityagupta1089 / EEP206-Verilog

ed-ke / 50-002_2D_Challenge_2018

neelabhro / Complex-Adder-with-SSD

Parrot043 / android_device_lenovo_a5000_adder_oreo

Parrot043 / android_vendor_lenovo_a5000_adder_oreo

PXVI / std_module

sujoyyyy / Computer-Architecture

minecraftdixit / Digital-ASIC-LAB

mosmduali / Telegram-Member-Adder

muznahsaqiib / 3-bit-adder-