zedboard

There are 3 repositories under zedboard topic.

bperez77 / xilinx_axidma
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
axi-dma axi-vdma dma-driver driver fpga fpga-dma linux-driver userspace-dma xilinx xilinx-axi-dma xilinx-axi-vdma zedboard
Language:C 438
MeowLucian / SDR_Matlab_OFDM_802.11a
:satellite: Using Software Designed Radio to transmit OFDM QPSK signals at 5 GHz
matlab zedboard ad9361 ofdm ieee80211a qpsk fmcomms3 fmcomms zynq xilinx analog-device 80211 sdr xilinx-zynq hardware radio gui preamble packets
Language:MATLAB 134
eliaskousk / parallella-riscv
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
parallella risc-v rocket-chip zynq linux-kernel zedboard gsoc gsoc-2016 rocket-core petalinux
Language:SystemVerilog 95
MeowLucian / SDR_Matlab_OFDM_802.11n
:satellite: Using Software Designed Radio to transmit MIMO-OFDM QPSK signals at 5 GHz
matlab zedboard ad9361 ofdm ieee80211 qpsk fmcomms fmcomms3 zynq xilinx analog-devices 80211 sdr xilinx-zynq hardware gui preamble radio mimo transmit-ofdm-signals
Language:MATLAB 77
WangXuan95 / Zynq-Tutorial
使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例
zedboard zynq zynq-7020 vivado petalinux soc-fpga block-design
Language:C 75
Kenji-Ishimaru / polyphony
3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
3d-graphics-rendering verilog fpga zedboard gpu realtime-rendering
Language:Verilog 60
DLX4 / zed_face
zedboard上基于FPGA+ARM的人脸识别智能监控系统。关键词：linux，zedboard，arm，fpga，人脸检测，人脸识别。
zedboard fpga face-recognition face-detection linux c
Language:C 48
jiafulow / zedboard-guide
zynq petalinux zedboard
35
MeowLucian / SDR_Matlab_LTE
:satellite: Using Software Designed Radio to transmit LTE downlink signals at 2.4 GHz
matlab zedboard ad9361 ofdm 64qam fmcomms3 fmcomms zynq xilinx analog-devices sdr xilinx-zynq hardware radio gui software-defined-radio iio
Language:MATLAB 35
MeowLucian / SDR_FM_Radio
:radio: Using Software Designed Radio to transmit & receive FM signal
simulink simulink-model zedboard ad9361 fmcomms fmcomms3 zynq xilinx analog-devices fm radio station xilinx-zynq modulation demodulation sdr
Language:MATLAB 34
FloyedShen / mnist_hls
Lenet for MNIST handwritten digit recognition using Vivado hls tool
mnist-hls hls vivado vivado-hls fpga-accelerator zedboard zynq
Language:Objective-C 33
MeowLucian / SDR_Matlab_OFDM_802.11a_16QAM
:satellite: Using Software Designed Radio to transmit OFDM 16QAM signals at 5 GHz
matlab zedboard ad9361 offline ieee80211 16qam fmccomm3 fmccomms zynq xilinx analog-devices 80211 sdr xilinx-zynq hardware radio preamble packets gui ofdm
Language:MATLAB 30
Goshik92 / SHA256Hasher
SHA-256 IP core for ZedBoard (Zynq SoC)
zynq xilinx zedboard soc vivado fpga sha256 systemverilog arm
Language:Verilog 29
sarthak268 / Embedded_Logic_and_Design
This repository contains all labs done as a part of the Embedded Logic and Design course.
verilog verilog-hdl verilog-programs verilog-project embedded-systems embedded-logic logic-circuit logic-programming embedded-c c vhdl vhdl-code zedboard xilinx xilinx-vivado xilinx-fpga xilinx-sdk arm vivado pmod
22
delhatch / Zynq_UDP
Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.
zedboard zynq udp
Language:C 19
mmattioli / ZedBoard-OLED
Driving the OLED display on the ZedBoard
oled zedboard zynq
Language:VHDL 19
delhatch / VGA_mem_mapped
Memory-mapped VGA display for Xilinx/Zynq/Zedboard, with demo code for using it.
zedboard vga vhdl mandelbrot
Language:VHDL 14
lvgl / lv_port_xilinx_zedboard_vitis
This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals
freertos lvgl mouse touchscreen usb vga zedboard digilent vitis vivado xilinx amd embedded ntp tcp
Language:C 14
splAcharya / DigitalOscilloscope_Zynq7000Soc
A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.
zedboard digital-oscilloscope xilinx-fpga xilinx-vivado zynq-7000 fpga-soc verilog-hdl embedded-systems
12
ugoleone / zedboard_image_processing_pipeline
FPGA based image processing pipeline using zedboard, able to accelerate openCV functions
zedboard ov7670 computer-vision image-processing fpga-soc vivado xilinx opencv xfopencv hls hls-video
Language:VHDL 10
bselimoglu / SoC-ZedBoard-Zynq-7000-Labs
Hardware and Software Co-design implementations
fsm zedboard zynq-7000 vivado-ip-integrator arm-cortex-a9 sdk zynq7-ps gpio axi ddr dma bram high-performance-port
9
delhatch / Zedboard_Mandel
Mandelbrot generator on the Zedboard. The image is output on the VGA port. Pure Verilog RTL, no ARM core.
verilog zedboard
Language:VHDL 8
eliaskousk / parallella-riscv-images
Parallella RISC-V Prebuilt Images
parallella board-parallella risc-v rocket-chip zedboard zynq linux-kernel gsoc gsoc-2016
8
HYSUM-TOBBETU / AES-Encryption-Verilog-Pipelined-Implementation-128bit
Device: Zedboard xc7z020clg484-1, Clock Rate: 319 MHz, Tool: Vivado 2018.3, Language: Verilog
aes-engine aes-wrapper clock-rate fpga matrix mds rcon-matrices sbox verilog vivado xor zedboard
Language:Verilog 8
Fivefold / SRCNN
Super Resolution Convolutional Neural Network (SRCNN) for Python/Torch, Numpy and Avnet's ZedBoard
cython python srcnn super-resolution torch zedboard
Language:VHDL 7
Fast-Fourier-Transform-in-C
neeraj1397 / Fast-Fourier-Transform-in-C
This repository contains the C code for ARM Implementation of FFT on Zynq-7000 APSoC from Xilinx.
fft xilinx-sdk zynq-7000 c zedboard
Language:C 7
zdzislaw-s / audio-processing
Simple audio processing with ADAU1761
adau1761 audio audio-processing bare-metal fpga hardware vivado xilinx zedboard zedboard-audio-jack zynq
Language:Tcl 7
delhatch / IIR_EQ
IIR audio filter in Verilog, running on Zedboard. Fractional integer coefficients.
verilog iir iir-filters iir-filter equalizer zedboard
Language:VHDL 6
Goshik92 / fsearch
FastSearch is a project intended to increase the speed of string searching by using the FPGA technology
fpga fpga-soc bitap vivado zynq verilog zedboard
Language:Verilog 6
zslwyuan / Zedboard_Intergrating_HLS_IP_AND_DDR
This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART.
zedboard hls vivado ddr tutorial
Language:VHDL 6
dougbrion / fpga-image-processing
Low latency FPGA based image processing (Zedboard)
fpga image-processing zedboard
Language:VHDL 5
Injabie3 / dj-board
SFU - ENSC 452 (Advanced Digital System Design) Term Project: The Ultimate DJ Board using a Zedboard. Also mirrored on SFU CSIL's GitLab.
simon-fraser-university embedded-systems vhdl xilinx-sdk xilinx-vivado xilinx zedboard c
Language:VHDL 5
mcagriaksoy / DegreeAdjustableRadar
Zynq ZedBoard SoC Lecture Final Project, degree adjustable ultrasonic sensor application
zynq vhdl zedboard c xilinx xilinx-fpga xilinx-vivado embedded-systems pwm pwm-driver pwm-servo-driver ultrasonic-sensor ultrasonic-sensor-distance
Language:VHDL 5
twosixlabs / ultrazed_dev
UltraZed Development
hardware-acceleration high-performance-computing fpga-soc-linux fpga-accelerator zynq zedboard
Language:C 5
arokasprz100 / HDL-Safe
Simple safe lock mechanism written in SystemVerilog.
systemverilog xilinx-vivado hdl zedboard zynq-7000 oled
Language:SystemVerilog 4
Inception-framework / debugger
A low-latency USB3-based JTAG debugger.
usb3 debugger fpga zynq zedboard
Language:VHDL 4

zedboard

bperez77 / xilinx_axidma

MeowLucian / SDR_Matlab_OFDM_802.11a

eliaskousk / parallella-riscv

MeowLucian / SDR_Matlab_OFDM_802.11n

WangXuan95 / Zynq-Tutorial

Kenji-Ishimaru / polyphony

DLX4 / zed_face

jiafulow / zedboard-guide

MeowLucian / SDR_Matlab_LTE

MeowLucian / SDR_FM_Radio

FloyedShen / mnist_hls

MeowLucian / SDR_Matlab_OFDM_802.11a_16QAM

Goshik92 / SHA256Hasher

sarthak268 / Embedded_Logic_and_Design

delhatch / Zynq_UDP

mmattioli / ZedBoard-OLED

delhatch / VGA_mem_mapped

lvgl / lv_port_xilinx_zedboard_vitis

splAcharya / DigitalOscilloscope_Zynq7000Soc

ugoleone / zedboard_image_processing_pipeline

bselimoglu / SoC-ZedBoard-Zynq-7000-Labs

delhatch / Zedboard_Mandel

eliaskousk / parallella-riscv-images

HYSUM-TOBBETU / AES-Encryption-Verilog-Pipelined-Implementation-128bit

Fivefold / SRCNN

neeraj1397 / Fast-Fourier-Transform-in-C

zdzislaw-s / audio-processing

delhatch / IIR_EQ

Goshik92 / fsearch

zslwyuan / Zedboard_Intergrating_HLS_IP_AND_DDR

dougbrion / fpga-image-processing

Injabie3 / dj-board

mcagriaksoy / DegreeAdjustableRadar

twosixlabs / ultrazed_dev

arokasprz100 / HDL-Safe

Inception-framework / debugger