cea-wind

SimpleTPU

A FPGA Based CNN accelerator, following Google's TPU V1.

LDPCC

Low Density Parity Check codes encoder and decoder, in particular for CCSDS standards.

hls_ldpc_dec

Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..

Viterbi-decoder

convolution codes simulation, decoder using the viterbi algorithm.

fpga_hls_program

fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

Cores-SweRV

SweRV EH1 core

fpga_parallel_computing

Parallel computing methods in FPGA using HLS

swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

blogs_pictures

cea-wind.github.io