clock-domain-crossing

There are 0 repository under clock-domain-crossing topic.

• hdl-modules

  hdl-modules / hdl-modules

  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

  alteraamdasicaxiaxi-litecdcclock-domain-crossingedaefinixfpgahardwareintelipmicrosemirtlvhdlvivadoxilinxasynchronous-fifofifo
  Language:VHDL 61

• akhan3 / async-fifo

  Asynchronous FIFO for transferring data between two asynchronous clock domains

  fpgaclock-domain-crossingfifo
  Language:Verilog 15

• AngeloJacobo / FPGA_Asynchronous_FIFO

  FIFO implementation with different clock domains for read and write.

  fpgaverilogfifoclock-domain-crossingasynchronous
  Language:Verilog 12

• hdl-util / clock-domain-crossing

  Utilities for clock-domain crossing with an FPGA

  clock-synchronizationclock-domain-crossingclock-domainsfpgasystemverilogverilog
  Language:SystemVerilog 5

• w-tr / clock-domain-crossing

  In digital design, it is sometimes necessary to transfer data from one clock domain to another. However because of the nature of how data is stored, there is a probability the transaction will have a setup and hold violation or data is lost because of the different between the domain speeds.

  cdcclockclock-domain-crossingsynchronizationclock-synchronizationclock-domainsclock-design
  Language:VHDL 5

• egk696 / InterChip_Bridge

  A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs

  fpgainterchip-bridgecommunication-protocolfault-tolerantfault-detectionasynchronousclock-domain-crossingnetwork-on-chipembedded-systems
  Language:VHDL 4

• takatz28 / FIFO-BIST

  Final project for the class "Application Specific Integrated Circuit Development"

  clock-domain-crossingsystemverilogfifobuilt-in-self-test
  Language:SystemVerilog 4