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Testbench for playing with the Endeavour protocol used by AMACv2.
Template for use with the build tool hdlmake, specifically set up for VHDL development and simulation.
Simplified, monocycle version of the LEGv8 processor designed by PCS Poli-USP and implemented in VHDL for Digital Systems II
use the liteeth core on the Nexys4 board without SoC