xilinx-zynq

There are 0 repository under xilinx-zynq topic.

MeowLucian / SDR_Matlab_OFDM_802.11a
:satellite: Using Software Designed Radio to transmit OFDM QPSK signals at 5 GHz
matlab zedboard ad9361 ofdm ieee80211a qpsk fmcomms3 fmcomms zynq xilinx analog-device 80211 sdr xilinx-zynq hardware radio gui preamble packets
Language:MATLAB 144
MeowLucian / SDR_Matlab_OFDM_802.11n
:satellite: Using Software Designed Radio to transmit MIMO-OFDM QPSK signals at 5 GHz
matlab zedboard ad9361 ofdm ieee80211 qpsk fmcomms fmcomms3 zynq xilinx analog-devices 80211 sdr xilinx-zynq hardware gui preamble radio mimo transmit-ofdm-signals
Language:MATLAB 82
MeowLucian / SDR_FM_Radio
:radio: Using Software Designed Radio to transmit & receive FM signal
simulink simulink-model zedboard ad9361 fmcomms fmcomms3 zynq xilinx analog-devices fm radio station xilinx-zynq modulation demodulation sdr
Language:MATLAB 38
MeowLucian / SDR_Matlab_LTE
:satellite: Using Software Designed Radio to transmit LTE downlink signals at 2.4 GHz
matlab zedboard ad9361 ofdm 64qam fmcomms3 fmcomms zynq xilinx analog-devices sdr xilinx-zynq hardware radio gui software-defined-radio iio
Language:MATLAB 37
MeowLucian / SDR_Matlab_OFDM_802.11a_16QAM
:satellite: Using Software Designed Radio to transmit OFDM 16QAM signals at 5 GHz
matlab zedboard ad9361 offline ieee80211 16qam fmccomm3 fmccomms zynq xilinx analog-devices 80211 sdr xilinx-zynq hardware radio preamble packets gui ofdm
Language:MATLAB 33
matthieu-labas / docker-petalinux
Docker image generation for generic Petalinux
petalinux-installers petalinux-docker petalinux xilinx-zynq xilinx docker-container docker docker-images docker-image
Language:Dockerfile 18
DYGV / HLS_FFT
Design of High-Level Synthesis of Xilinx FFT IP core via FFT library
fft high-level-synthesis xilinx-zynq fpga pynq
Language:Tcl 8
carlesfernandez / docker-petalinux
Docker image generation for Xilinx Petalinux Tools and Vivado
docker-petalinux xilinx-zynq vivado docker petalinux-installer petalinux-docker vivado-installer
Language:Dockerfile 7
systemviewinc / visual-system-integrator
Visual System Integrator - Accelerate your embedded development
fpga fpga-accelerator embedded integration vivado lenet high-level-synthesis hls sdsoc sdx accelerator cnn accelerate rapid rapid-development xilinx xilinx-zynq zynq virtex7 mpsoc
Language:Python 7
wubinary / two_stream_soc
SOC of two_stream action recognition on ZCU102
two-stream-cnn action-recognition quantization vivado-hls xilinx-zynq fpga-soc edge-detection
Language:Jupyter Notebook 7
ms0488638 / PYNQ_Burst_Test
This is a design for the test of AXI_HP on PYNQ-Z1 (as well as Z2, maybe)
pynq-z1 pynq-burst-test pynq xilinx-zynq
Language:Tcl 4
t-kuha / ultra96-unified
Ultra96 (v1 & v2) projects
zynq ultra96 vitis sdsoc mpsoc fpga xilinx xilinx-zynq
Language:C 3
urbanij / DDFS
Direct digital frequency synthesizer in Verilog and VHDL.
digital-design ddfs xilinx-zynq vhdl-coursework
Language:VHDL 3
AmirhoseinMasoumi / Zynq-Core-Board
Zynq Ultrascale+ Core Board
altium altium-designer pcb pcb-design xilinx xilinx-zynq zynq ultrascale-plus embedded-systems embedded-linux arm arm-cortex-a53
2
ckevar / IIR-Filter
IIR Filter for audio application
xilinx xilinx-zynq xilinx-fpga fpga fpga-programming vhdl vhdl-code vhdl-modules vhdl-examples iir iir-filter audio-processing audio-applications filter filtering filter-design digital-signal-processing digital-signals digital-signal-filtering digital-signal
Language:VHDL 2
dwij2812 / UART-Spectrum-Analyzer-for-Serial-Devices
The following Script can be used to generate certain mathematical functions on a micro controller or FPGA Device connected in serial based on the configuration selected by the the user and collect realtime data of the signal as generated by the device for spectrum analysis.
python3 matplotlib xilinx-vivado xilinx-zynq zedboard mplcursors numpy spectrum
Language:VHDL 2
JoseCVieira / JacobiMethod-HwSw-Architecture
Implementation of Jacobi method in a co-processing architecture Hw/Sw using FPGA (Field Programmable Gate Array) ZYBO Zynq-7000 Development Board for Co-Project Hw/Sw course.
co-design xilinx xilinx-fpga xilinx-vivado zybo-board jacobi jacobi-iteration xilinx-zynq vhdl c
Language:VHDL 2
kevinhikaruevans / blackboard-esp32
Embedded library for the on-board ESP32 on the RealDigital Blackboard
esp32 blackboard c microcontroller xilinx-zynq
Language:C 2
viktor-nikolov / ILI9488-Xilinx
ILI9488 TFT SPI display library for Xilinx SoC and FPGA
fpga ili9488 xilinx xilinx-fpga xilinx-zynq zynq zynq-7000
Language:C 2
wurmmi / fm-radio
Master thesis project - Comparing a FM Radio implementation in VHDL versus high-level synthesis (HLS).
xilinx-fpga xilinx-vivado xilinx-sdk xilinx-zynq xilinx-hls high-level-synthesis hls
Language:VHDL 2
cracked-machine / poky_zynqmp_generic_test
Testing meta-xilnx/poky layers with QEMU
docker xilinx-zynq yocto
Language:BitBake 1
ddurfeeEngineer / ad9361-iiostream-loopback
example of using iio to stream data from AD9361 with a coax cable loopback
ad9361 sdr vitis xilinx zed zedboard iio analog-devices xilinx-zynq zynq
Language:C 1
fsiddiqui85 / IPPro
The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.
datapath fpga hardware-acceleration image-processing microprocessor pipelined-processors processor risc softcore xilinx-zynq ippro
Language:Verilog 1
gitzhangzhao / petalinux_2017.04
配置好的 petalinux 2017.04 Docker 安装环境
docker petalinux xilinx-zynq
Language:Dockerfile 1
kuoyaoming93 / axi_uartlite_pynq
PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx
xilinx pynq pynq-z2 pynq-hardware-overlay pynq-z1 xilinx-zynq xilinx-vivado python uart axi jupyter-notebook
Language:Tcl 1
sefaburakokcu / finn-quantized-classification
Low-Precision Neural Networks for Classification on PYNQ with FINN
brevitas classification deep-learning finn neural-network pytorch quantization quantization-aware-training xilinx-zynq
Language:Python 1
thadoe / Digital_projects_in_Verilog_SystemC
Inference Design, Behavioral simulations, and Hardware Implementation.
vhdl verilog fpga-soc vivado xilinx-zynq quartus-prime systemc cpp c vivado-hls hardware
Language:Verilog 1
z1skgr / reconf-Computing__HLS
High Level synthesis of data transfer in Vivado, Vivado HLS
hls vivado-hls vivado simulation xilinx xilinx-vivado xilinx-zynq high-level-synthesis embedded-c embedded-systems data-structures data-system fifo-queue
Language:C++ 1
ArioKian / Xilinx-Zynq7000-PS-SLCR-Registers-Drivers
Zynq-7000 PS side drivers for SLCR Registers.
xilinx xilinx-fpga xilinx-sdk xilinx-vivado xilinx-zynq zynq zynq-7000 zynq-7010 zynq-7020 zynq-example-project
Language:C 0
ArioKian / Xilinx-Zynq7000-ZynqUltraScalePlus-PS-SdCard-Drivers
Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.
zynq-7000 zynq-7020 zynq-example-project zynq-ultrascale xilinx xilinx-fpga xilinx-sdk xilinx-vitis xilinx-vivado xilinx-zynq zynq zynq-7010
Language:C 0
efetunca / Zynq-7000-TFTP-Server
A TFTP server running on Zynq-7000
tftp tftp-server vitis xilinx xilinx-sdk xilinx-vitis xilinx-zynq zynq zynq-7000
Language:C 0
j-schacht / xilinx_zcu102_trustzone_demo
Tutorial and base project: TEE on AMD Zynq UltraScale+ using Arm TrustZone
aarch64 arm-trustzone fpga-soc fpga-soc-linux op-tee petalinux tee trustzone xilinx xilinx-zynq yocto amd-xilinx
Language:C 0
gonzafernan / cese-mys-zynq7
Microarquitecturas y Softcores - CESE - FIUBA
ip-core verilog verilog-hdl xilinx-vivado xilinx-zynq
Language:Verilog
JalalSayed1 / N-bit-Full-Adder
N-bit Full Adders implementation in VHDL
fpga full-adder vhdl vivado xilinx-zynq
Language:Tcl
JalalSayed1 / N-bit-Multiplier
N-bit Multiplier implementation in VHDL
fpga multiplier vhdl vivado xilinx-zynq
Language:VHDL
vacagonzalo / soc-workflow-firmware
Example workflow project for firmware development in Vitis.
automated-testing automation freertos repository vitis workflow xilinx xilinx-zynq
Language:C

xilinx-zynq

MeowLucian / SDR_Matlab_OFDM_802.11a

MeowLucian / SDR_Matlab_OFDM_802.11n

MeowLucian / SDR_FM_Radio

MeowLucian / SDR_Matlab_LTE

MeowLucian / SDR_Matlab_OFDM_802.11a_16QAM

matthieu-labas / docker-petalinux

DYGV / HLS_FFT

carlesfernandez / docker-petalinux

systemviewinc / visual-system-integrator

wubinary / two_stream_soc

ms0488638 / PYNQ_Burst_Test

t-kuha / ultra96-unified

urbanij / DDFS

AmirhoseinMasoumi / Zynq-Core-Board

ckevar / IIR-Filter

dwij2812 / UART-Spectrum-Analyzer-for-Serial-Devices

JoseCVieira / JacobiMethod-HwSw-Architecture

kevinhikaruevans / blackboard-esp32

viktor-nikolov / ILI9488-Xilinx

wurmmi / fm-radio

cracked-machine / poky_zynqmp_generic_test

ddurfeeEngineer / ad9361-iiostream-loopback

fsiddiqui85 / IPPro

gitzhangzhao / petalinux_2017.04

kuoyaoming93 / axi_uartlite_pynq

sefaburakokcu / finn-quantized-classification

thadoe / Digital_projects_in_Verilog_SystemC

z1skgr / reconf-Computing__HLS

ArioKian / Xilinx-Zynq7000-PS-SLCR-Registers-Drivers

ArioKian / Xilinx-Zynq7000-ZynqUltraScalePlus-PS-SdCard-Drivers

efetunca / Zynq-7000-TFTP-Server

j-schacht / xilinx_zcu102_trustzone_demo

gonzafernan / cese-mys-zynq7

JalalSayed1 / N-bit-Full-Adder

JalalSayed1 / N-bit-Multiplier

vacagonzalo / soc-workflow-firmware