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:satellite: Using Software Designed Radio to transmit OFDM QPSK signals at 5 GHz
:satellite: Using Software Designed Radio to transmit MIMO-OFDM QPSK signals at 5 GHz
:radio: Using Software Designed Radio to transmit & receive FM signal
:satellite: Using Software Designed Radio to transmit LTE downlink signals at 2.4 GHz
:satellite: Using Software Designed Radio to transmit OFDM 16QAM signals at 5 GHz
Docker image generation for generic Petalinux
Docker image generation for Xilinx Petalinux Tools and Vivado
Visual System Integrator - Accelerate your embedded development
SOC of two_stream action recognition on ZCU102
This is a design for the test of AXI_HP on PYNQ-Z1 (as well as Z2, maybe)
Zynq Ultrascale+ Core Board
IIR Filter for audio application
The following Script can be used to generate certain mathematical functions on a micro controller or FPGA Device connected in serial based on the configuration selected by the the user and collect realtime data of the signal as generated by the device for spectrum analysis.
Implementation of Jacobi method in a co-processing architecture Hw/Sw using FPGA (Field Programmable Gate Array) ZYBO Zynq-7000 Development Board for Co-Project Hw/Sw course.
Embedded library for the on-board ESP32 on the RealDigital Blackboard
ILI9488 TFT SPI display library for Xilinx SoC and FPGA
Master thesis project - Comparing a FM Radio implementation in VHDL versus high-level synthesis (HLS).
Testing meta-xilnx/poky layers with QEMU
example of using iio to stream data from AD9361 with a coax cable loopback
The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.
PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx
Low-Precision Neural Networks for Classification on PYNQ with FINN
Inference Design, Behavioral simulations, and Hardware Implementation.
High Level synthesis of data transfer in Vivado, Vivado HLS
Zynq-7000 PS side drivers for SLCR Registers.
Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.
A TFTP server running on Zynq-7000
Tutorial and base project: TEE on AMD Zynq UltraScale+ using Arm TrustZone
Microarquitecturas y Softcores - CESE - FIUBA
N-bit Full Adders implementation in VHDL
N-bit Multiplier implementation in VHDL
Example workflow project for firmware development in Vitis.