de10-lite

There are 10 repositories under de10-lite topic.

fpga-defender
w3arycod3r / fpga-defender
A recreation of Williams Defender 1981 arcade game for DE10-Lite FPGA dev board, written in VHDL.
fpga defender vhdl de10-lite quartus-prime
Language:VHDL 28
jeferal / Pong-FPGA
Pong game on FPGA Max 10 DE10-Lite, written in VHDL.
fpga vhdl pong max10 de10-lite vga-driver vga digital-electronics
Language:VHDL 12
timot3 / ECE385-Ethernet
ECE 385 Final Project -- Ethernet on MAX10 DE10-Lite FPGA and Nios II soft processor
nios2 nios-ii ethernet-shield ethernet fpga de10-lite
Language:Verilog 12
RomeoMe5 / De10-Lite_HDL_GPS
Simple verilog project with ability to connect to GPS module using UART and parse NMEA coordinates using finite state machine
gps de10-lite terasic-de10-lite quartus terasic miem hse uart ubx rtcm nmea neo-6 nmea-0183
Language:Verilog 8
FedorChervyakov / de10lite-hello-vga
VGA demo on the Terasic DE10-Lite FPGA board
de10-lite fpga makefile quartus vga
Language:VHDL 6
JosiahMendes / Autonomous-Rover
The Design and Implementation of an Autonomous Mars Rover that has full mapping, remote control and power management capabilities.
mars rover autonomous-driving smps esp32-arduino de10-lite arduino optical-flow reactjs nodejs
Language:C 6
pa-tiq / vending_machine
fpga de10-lite de10nano de10-nano quartus-prime quartus quartus-18-1 verilog verilog-project
Language:Verilog 6
protocol66 / FPGADefender
VHDL implementation of the Defender arcade game for DE-10 Lite FPGA. For ECE 4110 project.
fpga-game de10-lite
Language:VHDL 4
FedorChervyakov / de10lite-hello-adc
ADC demo on the Terasic DE10-Lite board with MAX10 FPGA
fpga adc de10-lite max10 quartus quartus-linux
3
graffou / agravic
Simulation platform that enables VHDL-style C++ coding. VCD generation for easy debug. VHDL code generation using C preprocessor. Simple risc-V rv32i SoC example, + Risc-V test suite and gcc bare-metal example. Linux (or WSL) / clang or gcc / risc-v toolchain / quartus required
vhdl simulator risc-v c-plus-plus vcd rtl gtkwave rtl-files arduino vidor fpga rtl-generation de10-lite
Language:C 3
JorgeAskur / Tic-Tac-Toe-FPGA
A recreation of the popular game Tic-Tac-Toe for the DE10-Lite FPGA dev board, in VHDL.
vhld de10-lite quartus-prime tic-tac-toe
Language:VHDL 3
riscygeek / quartus-make
This is a template for projects using the Quartus Prime suite with the DE10-Lite FPGA board.
de10-lite quartus quartus-prime makefile makefile-template template template-project
Language:Verilog 3
RomeoMe5 / Terasic-SMK-driver-use-cases
Terasic Servo Motor Kit (SMK) usage examples
smk gpio servo-motor-kit terasic miem hse fpga de10-lite pwm quartus
3
DavidKopalaCU / Verilog-ReactionTimer
A Reaction Timer for the DE10 Lite FPGA Written in Verilog HDL
verilog fpga de10-lite
Language:Verilog 2
jakujobi / BitBlaster_10bit_Processor
Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.
de10-lite digital-design fpga processor processor-design processors quartus quartus-prime systemverilog jakujobi
Language:SystemVerilog 2
kodachi77 / DE10liteDhrystone
Nios II Embedded System Dhrystone Test
de10-lite fpga-soc verilog fpga
Language:C 2
L4zy / DE10_Lite_ADC_UART
Using the DE10 Lite board, read an analogue signal (512 samples) and send the data out of a UART
vhdl python adc uart de10-lite
Language:VHDL 2
LockBall / floatfixlib_VHDL1993
ieee_proposed with names changed to floatfixlib to be compatible with Quartus Prime Lite and support fixed, float, etc.
vhdl floatfixlib ieee-proposed de10-lite modelsim quartus questa fixed float
Language:VHDL 2
tanb01 / MLED
VHDL Project 2018-2019: A university project to discover VHDL and the DE10 LITE 10M50DAF484C7G, just a "Moving Light Emitting Diode". The changing LED states between 10 LEDS creating the illusion that one LED is moving.
vhdl de10-lite led ece-paris
Language:VHDL 2
FedorChervyakov / de10lite-hello-nios2
Hello World from Nios 2
fpga qsys nios-ii makefile hello-world de10-lite
Language:Tcl 1
franciscoengenheiro / ticket-machine-fpga
Train ticket vending machine application designed for execution on an FPGA system. The application allows users to purchase tickets for various destinations and includes maintenance functionalities.
circuits de10-lite embedded-systems fpga hardware-designs kotlin logical-circuits signals-and-systems ticket-vending-machine vhdl college-project
Language:Kotlin 1
NestorDP / Verilog_by_examples
Source codes of examples from the book Verilog by Examples
de10-lite fpga max10 quartus verilog
Language:Verilog 1
austindriggs / simple-cpu-design
Design of a Simple CPU using the DE10-Lite FPGA from Intel and Quartus Prime
cpe cpu de10-lite quartus-prime vhdl wvu fpga
Language:VHDL 0
michaji / 4-bit-microprocessor-using-VHDL
A 4-bit Microprocessor that Performs Arithmetic Logic Operations
arithmetic de10-lite fpga-programming vhdl vhdl-code
Language:VHDL 0
aileneiioana / NiosII_HDL
altera avalon de10-lite eclipse fpga hdl nios-embedded-system nios-ii qsys quartus terasic-de10-lite verilog
Language:Verilog
Jideco / PongGameGroup22
This is a Pong Game created by Group 22 for EEE308 project, Electronics and Electrical Department, Obafemi Awolowo University.
de10-lite fpga-board vhdl
Language:VHDL
trilogysci / xasted
A 6 x 7 segment shooter game for fpga (DE10-Lite)
7-segment de10-lite fpga game
Language:Verilog

de10-lite

w3arycod3r / fpga-defender

jeferal / Pong-FPGA

timot3 / ECE385-Ethernet

RomeoMe5 / De10-Lite_HDL_GPS

FedorChervyakov / de10lite-hello-vga

JosiahMendes / Autonomous-Rover

pa-tiq / vending_machine

protocol66 / FPGADefender

FedorChervyakov / de10lite-hello-adc

graffou / agravic

JorgeAskur / Tic-Tac-Toe-FPGA

riscygeek / quartus-make

RomeoMe5 / Terasic-SMK-driver-use-cases

DavidKopalaCU / Verilog-ReactionTimer

jakujobi / BitBlaster_10bit_Processor

kodachi77 / DE10liteDhrystone

L4zy / DE10_Lite_ADC_UART

LockBall / floatfixlib_VHDL1993

tanb01 / MLED

FedorChervyakov / de10lite-hello-nios2

franciscoengenheiro / ticket-machine-fpga

NestorDP / Verilog_by_examples

austindriggs / simple-cpu-design

michaji / 4-bit-microprocessor-using-VHDL

aileneiioana / NiosII_HDL

Jideco / PongGameGroup22

trilogysci / xasted