synopsys-dc

There are 0 repository under synopsys-dc topic.

KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip
EE577b-Course-Project
networkonchip processor-design verilog-hdl synopsys-dc cadence-ncverilog cadence-conformal multiprocessor
Language:Verilog 13
gabrielganzer / RTL-PowerOptimization
Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
optimization dvs tcl polito design-vision voltage-scaling script primetime synopsys synopsys-dc project
Language:Verilog 11
OpenEDF / verilog-basic
learn the combinational and sequential logic circuit.
verilog fpga-programming fpga simulation simulator vhdl ice40up5k iverilog synopsys-dc synopsys-vcs
Language:SystemVerilog 10
tatan432 / AES_ENCODER
RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.
aes-encryption aes-128 encription rtl verilog-project digital digital-design ee4415 synthesis synopsys-dc synopsys-vcs
Language:Verilog 8
abdelazeem201 / ORCA
Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology
asic pnr rtl synopsys synopsys-dc synopsys-vcs synthesis upf verilog vhdl synopsys-iccii saed32nm asic-design fpga-soc hdl systemonchip
Language:Verilog 7
KevinWang96 / EE577b-HW
cadence-conformal modelsim synopsys-dc verilog-hdl
Language:Verilog 3
mohamedtareq24 / ASIC_implementation_of_PULPino_SoC
My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools
asic pnr risc-v synopsys-dc synopsys-iccii
Language:Verilog 3
kholoud0 / ASIC-Implementauion-of-CV32E40S-RISC-V-core-
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
asic implementation pnr synopsys synopsys-dc synopsys-iccii synthesis
Language:SystemVerilog 1

synopsys-dc

KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip

gabrielganzer / RTL-PowerOptimization

OpenEDF / verilog-basic

tatan432 / AES_ENCODER

abdelazeem201 / ORCA

KevinWang96 / EE577b-HW

mohamedtareq24 / ASIC_implementation_of_PULPino_SoC

kholoud0 / ASIC-Implementauion-of-CV32E40S-RISC-V-core-