multiplier

There are 0 repository under multiplier topic.

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
adder alu cadence-virtuoso cpu instruction-set-architecture multiplier processor processor-design simd verilog verilog-project
Language:Verilog 142
antonblanchard / vlsiffra
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
amaranth-hdl booth dadda physical-design verilog vlsi adder multiplier
Language:Python 118
suoglu / Fixed-Floating-Point-Adder-Multiplier
16-bit Adder Multiplier hardware on Digilent Basys 3
fpga vivado verilog hardware adder multiplier fixed-point floating-point binary16
Language:Verilog 81
greenelab / multi-plier
An unsupervised transfer learning approach for rare disease transcriptomics
bioinformatics-analysis gene-expression-signatures machine-learning multiplier plier rare-diseases analysis methodology dataset
Language:HTML 46
tharunchitipolu / Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
verilog dadda-tree vlsi vlsi-project vlsi-design multiplier hardware-description-language fulladder carry-save-adder dadda-multiplier tree-multipliers rtl wallace fast-multiplication
Language:Verilog 36
scale-lab / DRUM
The Verilog source code for DRUM approximate multiplier.
multiplier logic-synthesis approximate-circuits approximate-computing verilog
Language:Verilog 31
contributte / forms-multiplier
:repeat: Form multiplier & replicator for Nette Framework
contributte forms nette replicator multiplier
Language:PHP 28
RaulMurillo / Flo-Posit
Posit Arithmetic Cores generated with FloPoCo
adder flopoco multiplier posit posit-arithmetic unum vhdl
Language:VHDL 26
rcetin / booth_wallace_multiplier
Booth encoded Wallace tree multiplier
fpga multiplier booth-wallace verilog
Language:Verilog 18
mnb27 / Fast-Multipliers
32-bit Wallace and Dadda Tree Multiplier
multiplier verilog
Language:Verilog 11
gagan405 / WallTree
A VHDL code generator for wallace tree multiplier
hardware multiplier vhdl wallace-tree-multiplier
Language:VHDL 10
tharunchitipolu / Multi-operations-toolbox-with-baugh-wooley-multiplier
Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier
baugh-wooley digital digitalelectronics hardware-description-language multiplier verilog verilog-hdl vlsi vlsi-circuits
Language:Verilog 9
Hassan313 / Approximate-Multiplier
This repository contains approximate 8-bit multiplier Verilog code.
approximate-computing low-power multiplier runtime-configuration verilog
Language:Verilog 8
Saadia-Hassan / 8x8Multiplier-Using-Vedic-Mathematics
An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.
multiplier vedic-mathematics verilog-hdl xilinx-ise synthesis simulation adders
Language:Verilog 8
pub-calculator-io / lcm-calculator
Free WordPress Plugin: LCM calculator to find the LCM of two or more numbers. Shows solutions by prime factorization, common multiples, cake/ladder, GCF, division, and Venn diagram. www.calculator.io/lcm-calculator/
calculator calculator-plugin lcm lcm-calculator online-calculator plugin wordpress wordpress-plugin least-common-multiplier least-common-multiplier-calculator leastcommonmultiplier multiplier
Language:JavaScript 7
suoglu / Carry-Save-Multiplier
Parameterized and 4-bit carry save multiplier design
fpga hardware multiplier multipliers verilog
Language:Verilog 6
Centre-for-Hardware-Security / TTech-LIB
multiplier cryptography circuit asic fpga
Language:Verilog 5
gustavohb / booth-multiplier
VHDL implementation of the Booth's multiplication algorithm
algorithm booth booth-algorithm booths-algorithm multiplier vhdl
Language:VHDL 5
jpsimas / mbe-dadda-vhdl
Generator for unsigned n-bit modified Booth encoding Dadda tree multiplier code in VHDL written in C++. Based on https://github.com/HSOgawa/fast-multipliers/.
vhdl multiplier mbe modified booth cpp dadda tree
Language:C++ 5
SDibla / VHDL-Booth_Multiplier
Booth's algorithm is a procedure for the multiplication of two signed binary numbers in two's complement notation. This code is a structural\behavioral implementation of the N bit Booth's multiplier in VHDL.
booth-algorithm multiplier vhdl
Language:VHDL 5
suoglu / Integer-Multiplier-Hardware-Parameterized
Source code for pure combinational 16 bit integer multiplier hardware
hardware multiplier parameterized-multiplier verilog vivado
Language:Verilog 5
Ajay-Sai-Reddy / Vedic-Multiplier
An 4-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.
vedic-mathematics multiplier verilog-hdl ripple-carry-adder
Language:Verilog 3
himingway / Parallel_Multiplier
A Parallel Multiplier Using SystemVerilog HDL
systemverilog-hdl multiplier
Language:SystemVerilog 3
kotharipeddirajulu / 4bit_multiplier_using_4bit_full_adder_VHDL
This is a VHDL code for 4bit multiplier using 4bit full adder circuit structurally modelled.
vhdl-code vhdl 4bit multiplier 4bitadder fulladder
Language:VHDL 3
MohammadNiknam17 / Signed-4BIT-Binary-Multiplier_VHDL-FPGA
These are VHDL codes for a signed 4bit multiplier using 4bit adders. Base on Baugh-Wooley Method.
signed 4bit binary multiplier vhdl-code vhdl fpga fulladder halfadder full-adder baugh-wooley
Language:VHDL 3
negarhonarvar / Computer-Architecture
Implementation of Computer Architecture Consepts, Including Multiplier , Control Module, Verilog Elevator, Single cycle processor and mips pipeline with new forwarding unit.
control elevator mips-pipeline-processor multiplier singlecycle-processor
Language:Verilog 3
nicolavianello95 / mult32_MBE_dadda
Design and VHDL description of a 32bit multiplier using a Modified Booth Encoding and a Dadda CSA tree.
vhdl multiplier mbe booth booths-algorithm booth-algorithm booth-multiplier booth-encoding dadda dadda-tree csa modified-booth-algorithm modified-booth-encoding
Language:VHDL 3
anand873 / DigitalVLSI
This repository consists of verilog codes for Digital VLSI Lab (EC39004), IIT KGP.
shifter finite-state-machine multiplier booth-multiplier pipeline
Language:Verilog 2
andrea-varesio / smart-dca-backtest
Smart Dollar Cost Averaging backtest
backtest dca msci multiplier range sp500
Language:Python 2
arashsm79 / two-bit-multiplier
Two's complement two bit multiplier developed in Proteus
proteus logic-circuit logic logic-gates logic-design karnaugh-map twos-complement multiplier truth-table truth-tables gates
2
BlooketHeck / Claculators
A few calculators using python!
adding calculation calculations calulator divider multiplier multiply subtraction
Language:Python 2
GridSAT / CNF_FACT-MULT
CNF Generator for Factoring Problems
bdd cnf factoring multiplier sat-solver
Language:Haskell 2
SKpro-glitch / Parallel_Multiplier
Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
asic asic-design fpga fpga-programming multiplier parallel-multiplication register-transfer-level rtl rtl-design systemverilog systemverilog-test-bench verilog-hdl vlsi-design xilinx-vivado
Language:SystemVerilog 2
sourabhjain19 / Booth-s-Multiplier
COA OEE (ASM)
logisim booths-algorithm multiplier
Language:Assembly 2
ZeroDashZero / 32-bit-Multiplier-design-using-transistor-level-Digital-Gates
This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert
digital-gates 32-bit transistor-level spice cmos cppsim simulation fulladder multiplier logic-gates 16-bit digital-circuits vlsi vlsi-design
2
zpekic / sys_primegen
Signed / unsigned multiplier / divider used by a microcode-driven prime number generator
vhdl microcode fsm multiplier divider xilinx-ise fpga
Language:VHDL 2

multiplier

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

antonblanchard / vlsiffra

suoglu / Fixed-Floating-Point-Adder-Multiplier

greenelab / multi-plier

tharunchitipolu / Dadda-Multiplier-using-CSA

scale-lab / DRUM

contributte / forms-multiplier

RaulMurillo / Flo-Posit

rcetin / booth_wallace_multiplier

mnb27 / Fast-Multipliers

gagan405 / WallTree

tharunchitipolu / Multi-operations-toolbox-with-baugh-wooley-multiplier

Hassan313 / Approximate-Multiplier

Saadia-Hassan / 8x8Multiplier-Using-Vedic-Mathematics

pub-calculator-io / lcm-calculator

suoglu / Carry-Save-Multiplier

Centre-for-Hardware-Security / TTech-LIB

gustavohb / booth-multiplier

jpsimas / mbe-dadda-vhdl

SDibla / VHDL-Booth_Multiplier

suoglu / Integer-Multiplier-Hardware-Parameterized

Ajay-Sai-Reddy / Vedic-Multiplier

himingway / Parallel_Multiplier

kotharipeddirajulu / 4bit_multiplier_using_4bit_full_adder_VHDL

MohammadNiknam17 / Signed-4BIT-Binary-Multiplier_VHDL-FPGA

negarhonarvar / Computer-Architecture

nicolavianello95 / mult32_MBE_dadda

anand873 / DigitalVLSI

andrea-varesio / smart-dca-backtest

arashsm79 / two-bit-multiplier

BlooketHeck / Claculators

GridSAT / CNF_FACT-MULT

SKpro-glitch / Parallel_Multiplier

sourabhjain19 / Booth-s-Multiplier

ZeroDashZero / 32-bit-Multiplier-design-using-transistor-level-Digital-Gates

zpekic / sys_primegen