superscalar-cpu
There are 0 repository under superscalar-cpu topic.
HeliosXCore / HeliosXCore
HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.
Language:C++ 10Ghonimo / Perceptron-Combinational-Branch-Predictor-SimpleScalar-PSU-ECE587
Implementation of advanced branch predictors, including Perceptron and Combinational Two-Level Adaptive Predictors, within the SimpleScalar simulator. Showcases enhancements in prediction accuracy and dynamic branch prediction techniques. This is a project for PSU ECE 587: Advanced Computer Architecture
Language:C 2cepdnaclk / e16-Co502-SuperScalar-CPU-With-Dynamic-Sheduling
Implementation of a Superscalar CPU with Dynamic Scheduling which support RISC-V standard ISA with standard 'M' Extention
SoumyadeepChatterjee / Superscalar-OOO-Pipeline-Sim
Instructions Per Count (IPC) Study on 9-Stage Supescalar Pipeline with Out-of-Order Execution
Language:C++ 1vbogdev / vbn-Riscv
An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.
Language:SystemVerilog 1chylaa / superscalar-arch-sim
Simulator of pipelined, superscalar processor core based on RISC-V ISA
Language:C# 0kkadzielna / cpusim
A simple cpu simulator and an analyisis of its performance.
Language:Python 0rohankalbag / superscalar-risc
Course Project - Advanced Computer Architecture - Autumn Semester 2022 - Indian Institute of Technology Bombay
Language:VHDL 0sebastian-wardzinski / computer-architecture
ECE552: Computer Architecture — Fall 2020.
Language:C 0