verilog-code

There are 17 repositories under verilog-code topic.

snbk001 / Verilog-Design-Examples
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier
verilog testbenches verilog-design verilog-code verilog-hdl verilog-programs verilog-project self-checking
Language:Verilog 72
benitoss / UnAmiga
Implementation of Amiga 500/1200 in Altera Cyclone IV FPGA
verilog-code
Language:VHDL 50
TheSUPERCD / 8bit_MicroComputer_Verilog
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
verilog verilog-hdl verilog-project verilog-code iverilog 8bit ben-eater ben-eaters-cpu
Language:Verilog 47
Arjun-Narula / Traffic-Light-Controller-using-Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
verilog verilog-hdl verilog-project verilog-code verilog-programs verilog-simulator vivado vivado-hls vivado-simulator traffic traffic-light traffic-sign-recognition
Language:JavaScript 37
mihir8181 / VerilogHDL-Codes
Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
verilog verilog-project verilog-code verilog-programs verilog-hdl n-bit-alu counter fsm moore-machine-code mealy-machine-code verilogvalidation testbenches design-under-test fifo asynchronous asynchronous-fifo fifo-buffer fifo-verilog
Language:Verilog 34
getting-started-with-verilog
aklsh / getting-started-with-verilog
Verilog modules for beginners
verilog verilog-hdl verilog-code verilog-snippets open-source
Language:Verilog 22
verilog-rle
geraked / verilog-rle
Verilog Implementation of Run Length Encoding for RGB Image Compression
verilog fpga ise rle rle-compression-algorithm compression-algorithm verilog-hdl verilog-code image-compression matlab fpga-programming xilinx xilinx-fpga run-length-encoding image-processing geraked rabist student-project yazd-university computer-engineering
Language:Verilog 22
aditeyabaral / DDCO-Lab-UE18CS207
A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.
verilog icarus-verilog digital-design computer-organization verilog-code logic-programming
Language:Verilog 16
aut-ce / CE202-LC-Lab-Manual
Manual and Template Sources of Logic Circuit Laboratory (Verilog Templates)
verilog-code logic-circuit-laboratory homework-assignments
Language:C 16
djzenma / RV32IC-CPU
Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
cpu risc-v riscv32 risc verilog rv32i rv32imc riscv32im risc-processor riscv-simulator verilog-hdl verilog-code verilog-snippets hdl pipeline-processor pipeline-cpu
Language:Verilog 14
jge162 / verilog_compiler
Verilog_Compiler is now available in GitHub Marketplace! This tool can quickly compile Verilog code and check for errors, making it an essential tool for developers.
compiler fast github-action verilog verilog-code verilog-compiler verilog-hdl verilog-scanner
Language:Verilog 13
vasanthkumar18 / Cache-Compression
Cache compression using BASE-DELTA-IMMEDIATE process in verilog
cache cache-compression bdi-model project verilog-project verilog-code hardware-project hacktoberfest hacktoberfest2021
Language:Verilog 10
Sanskar777 / QRS-peak-detection-in-ECG-signals-using-verilog
ecg-signal ecg-qrs-detection curve-length-transform verilog-code qrs-peak-detection
Language:Verilog 9
mahdizynali / verilog-digital-circuit-codes
simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)
arithmatic fulladder fullsubtractor halfadder halfsubtractor logic multiplexer mux shift-left shift-register shift-right verilog verilog-code
Language:Verilog 8
pratikbhuran / Voting_Machine
Voting machine implemented in verilog
verilog-hdl verilog verilog-project verilog-code voting-machine voting-system
Language:Verilog 8
EhsanShahbazii / Digital-VLSI-System-Design-Projects
سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر
verilog verilog-code verilog-components verilog-project vlsi
Language:Verilog 7
sts08015 / HDLBits_solution
My own HDLBits solution :)
verilog verilog-code verilog-hdl hdlbits hdlbitssolution
Language:Verilog 6
vSasakiv / RV32I_Processor
Risc-V 32i processor written in the Verilog HDL
risc-v riscv32 riscv32i verilog verilog-code verilog-hdl verilog-project
Language:Verilog 6
daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
clock-generator hdl rtl spi spi-interface spi-master spi-protocol spi-slave testbench verilog verilog-code verilog-hdl verilog-project verilog-rtl-model wishbone wishbone-master
Language:Verilog 5
mseminatore / fpgacoding
Source code companion to the fpgacoding.com blog
fpga verilog verilog-hdl verilog-code
5
mongrelgem / UART-RTL-Physical-Design
Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2
uart uart-interface verilog verilog-code hardware-designs layout
Language:Perl 4
University-projects
trojanink / University-projects
Some of the projects I developed during my studies at University of Thessaly, Electrical & Computer Engineering Dpt.
university computer-engineering-dpt studies projects c c-language c-language-math homework assembly assembly-language assembly-language-programming verilog-project verilog-code verilog-components verilog
Language:C 4
ukashasohail / MIPS_32bit_SCDP_Verilog
An implementation of 32-bits MIPS Single Cycle Datapath in Verilog HDL.
mips mips-assembly mips-architecture verilog verilog-hdl verilog-project verilog-code mips32
Language:Verilog 4
Dhruv0Upadhyay / 100_Days_of_RTL
100 Days challenge to improve digital desinging using languages like Verilog & SystemVerilog
ram verilog verilog-code verilog-hdl verilog-project vivado xilinx-vivado
Language:Verilog 3
mircea-pavel-anton / VHDL-Decryption
A small decryption module, written in Verilog, as a university assignment.
verilog verilog-hdl verilog-code verilog-project decryption caesar-cipher caesar-cipher-algorithm scytale-cipher zigzag-cipher fence-cipher
Language:Verilog 3
PXVI / std_module
All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.
verilog-modules verilog-code rtl shifter siso adder subtractor fifo mux encoder decoder lfsr
Language:Verilog 3
GirloftheLimberlost / DigitalLockFPGA
FPGA Digital Lock System with 7 Segment LED Display - Password changeable (Hexadecimal Passwords)
verilog verilog-project verilog-code fpga seven-segments-display led
2
hwlabnitc.github.io
hwlabnitc / hwlabnitc.github.io
Main website of the HW Lab guide by NITC
assembly mips single-cycle-processor tutorial verilog verilog-code verilog-hdl
2
iancraz / EV21-Processor
EV21 RISC Processor Design
processor processor-architecture risc quartus-prime cyclone-iv altera altera-fpga cyclone cyclone-v hdl pipeline verilog verilog-code verilog-hdl verilog-project
Language:Verilog 2
janilaunonen / iCEblink40-examples
Simple example programs for the Lattice iCEblink40-HX1K Evaluation Kit in Verilog for fun and learning.
verilog-code fpga-board examples open-source-toolkits lattice ice40hx1k fpga
Language:Verilog 2
ozlemkayikcii / VerilogCourse
What I learned in the Verilog course includes the assignments I completed and laboratory files.
verilog verilog-code verilog-project
Language:Verilog 2
YajanaRao / Verilog
Verilog Programs
verilog ise vending-machine data-flow structural behavioral mux flipflop moore-machine state-machine tasks functions hdl fsm mealy-machine-code moore-machine-code verilog-hdl verilog-project verilog-code verilog-programs
Language:Verilog 2
aula9 / Computer-Design-of-Electronic-Circuits-Lectures
cad cmos lecture-notes lecture-slides verilog verilog-code verilog-hdl
1
JN513 / estudos_verilog
Exemplos feito em verilog para estudos
fpga fpga-programming hardware verilog verilog-code verilog-hdl
Language:Verilog 1
Raveem13 / HDLbits-practice-solution
This is a repository containing my solutions to the problem statements given on HDLBits website.
hardware-description-language hdl hdlbits hdlbitssolution verilog verilog-code verilog-programs digitallogic fpga-programming logicdesign
Language:Verilog 1
samiyaalizaidi / Direct-Digital-Synthesizer
Direct Digital Synthesizer for Generating Sine Waves using Verilog HDL
digital-system-design direct-digital-synthesizer sine-wave-generator verilog-code verilog-hdl
Language:Verilog 1

verilog-code

snbk001 / Verilog-Design-Examples

benitoss / UnAmiga

TheSUPERCD / 8bit_MicroComputer_Verilog

Arjun-Narula / Traffic-Light-Controller-using-Verilog

mihir8181 / VerilogHDL-Codes

aklsh / getting-started-with-verilog

geraked / verilog-rle

aditeyabaral / DDCO-Lab-UE18CS207

aut-ce / CE202-LC-Lab-Manual

djzenma / RV32IC-CPU

jge162 / verilog_compiler

vasanthkumar18 / Cache-Compression

Sanskar777 / QRS-peak-detection-in-ECG-signals-using-verilog

mahdizynali / verilog-digital-circuit-codes

pratikbhuran / Voting_Machine

EhsanShahbazii / Digital-VLSI-System-Design-Projects

sts08015 / HDLBits_solution

vSasakiv / RV32I_Processor

daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules

mseminatore / fpgacoding

mongrelgem / UART-RTL-Physical-Design

trojanink / University-projects

ukashasohail / MIPS_32bit_SCDP_Verilog

Dhruv0Upadhyay / 100_Days_of_RTL

mircea-pavel-anton / VHDL-Decryption

PXVI / std_module

GirloftheLimberlost / DigitalLockFPGA

hwlabnitc / hwlabnitc.github.io

iancraz / EV21-Processor

janilaunonen / iCEblink40-examples

ozlemkayikcii / VerilogCourse

YajanaRao / Verilog

aula9 / Computer-Design-of-Electronic-Circuits-Lectures

JN513 / estudos_verilog

Raveem13 / HDLbits-practice-solution

samiyaalizaidi / Direct-Digital-Synthesizer