mips-processor

There are 1 repository under mips-processor topic.

mhyousefi / MIPS-pipeline-processor
A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
mips-processor verilog pipeline forwarding-unit hazard-detection computer-architecture
Language:Verilog 145
neelkshah / MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog
computer-architecture computer-organization computer-organisation microprocessor microprocessors bits-pilani verilog verilog-hdl verilog-project verilog-programs verilog-components verilog-snippets verilog-simulator mips-processor mips-architecture mips-instructions
Language:Verilog 112
aeris170 / MARS-Theme-Engine
It's all coming back into focus!
mars-theme-engine mars mips mips-assembly mips-architecture mips-simulator mips-processor
Language:Java 79
alirezakay / RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
cpu cpu-model cpu-architecture processor-design processor-architecture mips-processor isa instruction-set-architecture multi-cycle risc-processor vhdl vhdl-code vhdl-modules
Language:VHDL 26
Ingenic-community / linux
Linux kernel source tree with the latest features and modifications to unleash the full potential of Ingenic processors.
ingenic linux linux-kernel x1000 x2000 jz4780 x1501 mips mips-architecture mips-processor mips32
Language:C 24
asm-snippets
edoardottt / asm-snippets
Some of my assembly code (examples, iterative and recursive algorithms) from Computer's Architecture course in Sapienza University, CS Bachelor's Degree :floppy_disk:
asm assembly assembler assembly-language-programming assembly-x86 assemblyscript algorithms assembly-language mips-architecture asm-mars recursive-algorithms computer-hardware processor storage parallelism cpu mips mips-assembly mips-processor
Language:Assembly 18
prantoamt / 16bit_processor_design
hardware-designs processor processor-architecture logisim computer-architecture simulation computer-design-and-implementation cpu cse332 cse mips mips-assembly mips-architecture mips-simulator mips-processor mips-assembler mips-language
12
hakula139 / MIPS-CPU
A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog
mips-processor systemverilog cache branch-prediction pipeline
Language:SystemVerilog 9
jasonlovescoding / MIPS32CPU-5stage-pipelined
A 5-stage pipelined mips32 processor
verilog buaa course-project mips-processor
Language:Verilog 9
MARS-UCA
holden-davis-uca / MARS-UCA
Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.
mips mips-assembly mips-architecture mips-simulator mips32 mips-processor mips32cpu mips-assembler mips-instructions mips-language java
Language:HTML 7
JosiahMendes / MIPS32-T501
A low power, high performance 32-bit, 5-cycle MIPS core that implements a subset of instructions.
mips32 mips-assembler verilog systemverilog mips-processor
Language:Verilog 7
alabarjasteh / fum-mips
MIPS simulator written in Go
mips mips-simulator mips-processor computer-architecture concurrent-programming cpu isa
Language:Go 6
MipsStaticStackAnalyzer
SentinelSw / MipsStaticStackAnalyzer
An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler
stack stackoverflow stack-overflow statistics static-analysis static static-analyzer static-code-analysis microchip microchippic32 microchip-pic xc32 mips mips32 mips-architecture mips32cpu mips-processor mips-assembly mips-instructions analyzer
Language:C 6
flozzone / DDCA
Solution for the assignment in Digital Design and Computer Architecture course including test benches running faster than official nightly tests.
vhdl mips-processor
Language:VHDL 5
Gripnook / mips-pipelined-processor
A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.
mips-processor pipelining forwarding caching branch-prediction
Language:VHDL 5
mongrelgem / cMIPS
A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
mips-processor mips-architecture processor vhdl-code verilog-hdl hardware-designs
Language:Verilog 5
yasnakateb / MIPSProcessor
🔮 A 32-bit MIPS Processor Implementation in Verilog HDL
cpu mips-processor multicycle xilinx
Language:Verilog 5
yasnakateb / PipelinedMIPS
🔮 A 16-bit MIPS Processor Implementation in Verilog HDL
cpu mips-processor mips mips-pipeline pipeline iverilog icarus-verilog verilog verilog-hdl
Language:Verilog 5
z64me / minimips64
the tiniest MIPS R4300i assembler and disassembler
mips-processor mips mips-assembler mips-instructions c nintendo-64
Language:C 5
aeris170 / Dark-Side-of-MARS
DEPRECATED!!! An (almost) fully functional theme engine for MARS.
mars mips mips-assembly mips-architecture mips-simulator mips-processor
Language:Java 4
cwalk / Mini-Processor-Simulator
Core part of a mini processor simulator called MySPIM using the C language on a Unix/Linux platform. MySPIM demonstrates some functions of the MIPS processor as well as the principle of separating the data-path from the control signals of the MIPS processor. The MySPIM simulator reads in a file containing MIPS machine code (in a specified the format) and simulates what MIPS does cycle-by-cycle (single-cycle data path).
mips-processor mips mini-processor-simulator c
Language:C 4
daltonbr / MIPS
simulator of a MIPS processor in C
mips mips-processor simulator
Language:C 4
nimaiji / MIPS-Pipeline-CPU
💻 MIPS Pipeline Processor simulator
cpu mips mips-assembly mips-simulator mips32 mips-processor mips-language processor-simulator processor-architecture
Language:Python 4
psh4607 / 32-bit-MIPS-Processor-Pipeline
A 32-bit MIPS processor developed in Verilog based on pipeline
mips verilog mips-assembly processor mips-processor mips32 mips-architecture
Language:C 4
anupbhowmik / Computer-Architecture-CSE-306
This is a repository containing all the simulations and reports of CSE-306 Computer Architecture Sessional.
arithmetic-logic-unit floating-point-adder mips-processor
Language:C++ 3
AbdallahReda / MIPSProcessor
Verilog Description for a 32bit MIPS Processor
mips32cpu mips-processor mips-assembly mips-architecture
Language:Verilog 2
akankshac-073 / MIPS-5-stage-pipelined-control-and-datapath
Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control, hazard detection and stalling units are also implemented to improve the efficiency of the pipeline. The designed processor can be tested by initializing the instruction memory with test instructions and obtaining the corresponding register contents by generating waveforms on ModelSim.
computer-architecture mips-processor pipelined-processors verilog mips-architecture mips-pipline-processor-verilog mips32
Language:Verilog 2
aminhm / MIPS-CPU-simulator
mips mips-architecture mips-simulator mips-processor mips-instructions mips32 cpu cpu-emulator python
Language:Python 2
arlotfi79 / MIPS-Processor
A 32-bit MIPS Processor Implementation in Verilog HDL
mips-processor multicycle pipeline verilog-hdl xilinx
Language:Verilog 2
cgsdfc / mips-pipeline-cpu.verilog
A simple five-stage pipeline MIPS CPU in Verilog.
assembly mips-processor pipeline-cpu verilog-hdl buaa-co mips
Language:Assembly 2
fardinanam / CSE-306-Computer-Architecture-Sessional
Assignments done in CSE306 course offered by CSE, BUET
arithmetic-logic-unit computer-architecture floating-point-adder mips-processor simulation
Language:C++ 2
Mips-MultiCycle
kalhorghazal / Mips-MultiCycle
Mips Multi-Cycle, Computer Architecture course, University of Tehran
mips-architecture mips multi-cycle-processor verilog-hdl mips-processor
Language:SystemVerilog 2
lone0 / buildroot-x2000
Buildroot for Halley5, the evaluation board for Ingenic X2000 SoC
ingenic mips mips-processor mips32 mips32cpu x2000 xburst
Language:Makefile 2
mcai / heo
Heo is a cycle-accurate multicore architectural simulator written in Go.
multicore-cpu multicore-processors simulator computer-architecture architectural-simulation golang cycle-accurate mips-simulator mips mips-processor
Language:C 2
NSU-ACM-SC / 16bit_processor_design
hardware-designs logisim simula processor-architecture processor mips-simulator mips mips-assembly mips-processor mips-assembler
2
YanzheL / mips_soft_cpu
Course project for Computer Design and Practice at HIT.
mips-assembly mips-processor mips32 verilog-project
Language:VHDL 2

mips-processor

mhyousefi / MIPS-pipeline-processor

neelkshah / MIPS-Processor

aeris170 / MARS-Theme-Engine

alirezakay / RISC-CPU

Ingenic-community / linux

edoardottt / asm-snippets

prantoamt / 16bit_processor_design

hakula139 / MIPS-CPU

jasonlovescoding / MIPS32CPU-5stage-pipelined

holden-davis-uca / MARS-UCA

JosiahMendes / MIPS32-T501

alabarjasteh / fum-mips

SentinelSw / MipsStaticStackAnalyzer

flozzone / DDCA

Gripnook / mips-pipelined-processor

mongrelgem / cMIPS

yasnakateb / MIPSProcessor

yasnakateb / PipelinedMIPS

z64me / minimips64

aeris170 / Dark-Side-of-MARS

cwalk / Mini-Processor-Simulator

daltonbr / MIPS

nimaiji / MIPS-Pipeline-CPU

psh4607 / 32-bit-MIPS-Processor-Pipeline

anupbhowmik / Computer-Architecture-CSE-306

AbdallahReda / MIPSProcessor

akankshac-073 / MIPS-5-stage-pipelined-control-and-datapath

aminhm / MIPS-CPU-simulator

arlotfi79 / MIPS-Processor

cgsdfc / mips-pipeline-cpu.verilog

fardinanam / CSE-306-Computer-Architecture-Sessional

kalhorghazal / Mips-MultiCycle

lone0 / buildroot-x2000

mcai / heo

NSU-ACM-SC / 16bit_processor_design

YanzheL / mips_soft_cpu