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Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.
CMake modules for building Bluespec targets
Bluespec SystemVerilog language definition for the LaTeX listings package
A collection of activation functions implemented in Bluespec for integration with hardware designs, ensuring IEEE 754 compliance
Bluespec System Verilog syntax highlighting for Notepad++