zslwyuan

Tingyuan LIANG's repositories

Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

Language:VerilogGPL-3.0111 6 3

LLVM-9.0-Learner-Tutorial

A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accomplish a complete project for FPGA High-Level Synthesis with it.

Language:C++GPL-3.0100 5 3

AMF-Placer

AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)

Language:C++Apache-2.089 4 11

Light-HLS

Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)

Language:C++GPL-3.057 6 6

PAAS_V1.0

PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems

Language:AdaGPL-3.041 3 3

LLVM-11-Tutorials

A blog for LLVM(v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM.

Language:C++GPL-3.011 30

AutoCellLibX

AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining

Language:PythonApache-2.09 2 1

EDA-wiki

EDA wiki

Language:Shell1 10

Hi-ClockFlow

Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis

1 20

astran

ASTRAN - Automatic Synthesis of Transistor Networks

Language:CBSD-2-Clause010

Attachments

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Catch2

A modern, C++-native, test framework for unit-tests, TDD and BDD - using C++14, C++17 and later (C++11 support is in v2.x branch, and C++03 on the Catch1.x branch)

Language:C++BSL-1.0000

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Language:CNOASSERTION010

cloc-badge-action

Language:Shell010

COFFE

Language:Python000

constellation

A Chisel RTL generator for network-on-chip interconnects

Language:ScalaBSD-3-Clause000

docker-wechat

DoChat is a Dockerized WeChat (盒装微信) PC Windows Client for Linux

Language:ShellApache-2.0010

doxygen-action

GitHub Action for generating Doxygen documentation for your projects.

Language:ShellMIT000

echarts

Apache ECharts is a powerful, interactive charting and data visualization library for browser

Language:TypeScriptApache-2.0000

f4pga

FOSS Flow For FPGA

Language:PythonApache-2.0000

gmsh-doc

How to read the source code of gmsh

Language:C++NOASSERTION010

i-octee

GPL-2.0000

Kratos

Kratos Multiphysics (A.K.A Kratos) is a framework for building parallel multi-disciplinary simulation software. Modularity, extensibility and HPC are the main objectives. Kratos has BSD license and is written in C++ with extensive Python interface.

NOASSERTION000