A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
This project is implemented in VHDL language with ISE simulator software with a particular specifications.
Relevant course for this project could be computer architecture.
These codes here in github, are just the vhdl and wave files.
If you wanna get the complete project codes, built with ISE go here, find the project title and download the full one.
here is a fairly complete documentaion written in Persian and also English languages: document
This project is licensed under the MIT License - see the LICENSE file for details