instruction-set-architecture

There are 4 repositories under instruction-set-architecture topic.

hlorenzi / customasm
💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/
assembly assembly-language assembler instruction-set instruction-set-architecture processor-architecture microprocessor bytecode bytecode-compiler compiler customizable custom virtual-machine vm machine-code webassembly user-defined asm rust rust-lang
Language:Rust 998
Maratyszcza / Opcodes
Database of CPU Opcodes
instructions instruction-set-architecture x86 x86-64 opcodes
Language:Python 259
zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
simd processor verilog processor-design verilog-project multiplier adder instruction-set-architecture cadence-virtuoso cpu alu
Language:Verilog 142
mikeroyal / AMX-Guide
Advanced Matrix Extensions (AMX) Guide
advancedmatrixextensions amx cpu tilematrixset instruction-set-architecture accelerator datastreaming dsa fpga intel awesome awesome-list awesome-resources awesome-readme
Language:C++ 105
gabrieldim / Assembly-MIPS-Instruction-Set
Assembly program with the MIPS instruction set
mips-assembly mips assembly assembly-language instruction-set-architecture
Language:Assembly 99
scarv / xcrypto
XCrypto: a cryptographic ISE for RISC-V
risc-v riscv verilog formal-verification yosys icarus-verilog hardware hardware-acceleration cryptography instruction-set-architecture open-source mit-license crypto cpu ise research-project xcrypto
Language:Verilog 92
edanor / umesimd
UME::SIMD A library for explicit simd vectorization.
avx simd scalar-types performance-tuning vectorization benchmark vector avx2 avx512 neon altivec instruction-set-architecture code-generation cpp cpp11 cpp14 cpp17 simd-instructions simd-programming ume
Language:C++ 91
AluVM / aluvm
AluVM: RISC functional machine base implementation
virtual-machine instruction-set-architecture edge-computing functional-programming embedded-systems risc microcontrollers smart-contracts blockchain rust
Language:Rust 63
riscv-assembler
kcelebi / riscv-assembler
RISC-V Assembly code assembler package for Python.
assembly-language-programming risc-v instruction-set-architecture python riscv-assembler
Language:Python 54
TomerAberbach / mano-simulator
🖥️ An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer.
mano hardware-simulator assembler mano-simulator mano-machine computer-architecture java java-8 java8 simulator javafx javafx-8 javafx-application java-application editor text-editor hardware-simulation 16bit architecture instruction-set-architecture
Language:Java 41
sjohann81 / hf-risc
HF-RISC SoC
mpsoc embedded-systems hf-risc processor soc computer-architecture risc-v mips instruction-set-architecture instruction-set-simulator
Language:C 39
Nibbling-bits
aofarmakis / Nibbling-bits
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
assembler assembly hardware-description-language processor-design verilog computer-architecture computer-organization instruction-set-architecture single-cycle-processor
Language:Verilog 36
alirezakay / RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
cpu cpu-model cpu-architecture processor-design processor-architecture mips-processor isa instruction-set-architecture multi-cycle risc-processor vhdl vhdl-code vhdl-modules
Language:VHDL 29
scarv / scarv-cpu
SCARV: a side-channel hardened RISC-V platform
riscv riscv32 xcrypto formal-verification yosys cryptography open-source mit-license crypto cpu ise instruction-set-architecture research-project verilator verilog
Language:Verilog 27
dmjio / LC3
:floppy_disk: The LC3 virtual machine
lc3 haskell virtual-machine assembly opcodes instruction-set-architecture
Language:Haskell 24
aphelion
orbit-systems / aphelion
64-bit RISC CPU Architecture
instruction-set-architecture isa 64-bit instruction-set risc
Language:C 21
sdasgup3 / parallel-processor-design
Super scalar Processor design
verilog-hdl processor verilog processor-architecture processor-simulator instruction-set-architecture superscalar pipeline-processor pipeline-cpu assembler flex bison parallel-computing instruction-level-parallelism mnemonics forwarding bypassing branch-prediction instruction-set opcode
Language:Verilog 21
ryukzak / wrench
Wrench - is a tool for educating computer architecture.
education instruction-set-architecture university-course
Language:Haskell 20
yonseicasl / Kite
Kite: Architecture Simulator for RISC-V Instruction Set
risc-v simulator architecture five-stage pipeline model education assembly computer-architecture microarchitecture pipelining branch-prediction cache instruction-set instruction-set-architecture memory instruction-dependency
Language:C++ 19
celebi-pkg / riscv-assembler
RISC-V Assembly code assembler package for Python.
assembler assembly instruction-set-architecture python risc-v riscv riscv-assembler
Language:Assembly 18
katamaran-project / katamaran
Katamaran is a semi-automated separation logic verifier for the Sail specification language. It works on an embedded version of Sail called μSail and verifies separation logic-based contracts of functions by generating (succinct) first-order verification conditions.
instruction-set-architecture verification separation-logic symbolic-execution
Language:Rocq Prover 18
HarieshAnbalagan / RV32I
Minimalistic RV32I RISC-V Processor in System Verilog
processor risc-v rv32i computer-architecture digital-design fpga instruction-set-architecture simulations systemverilog
Language:SystemVerilog 14
mnurczynski / pi
My very own CPU architecture! Emulator availible!
architecture assembly assembly-language computer-architecture cpp cpp-programming emulation emulator-development emulators hardware hardware-design instruction-set-architecture microcode digital digital-design digital-design-and-computer-organization
Language:C++ 14
agicy / buptAsgmt-organization
北京邮电大学 2023-2024 春季学期《计算机组成原理》课程作业的相关文档
bus-system computer-organization cpu-organization instruction-set-architecture peripheral-devices storage-systems
12
Mograsim
Mograsim-Team / Mograsim
Modular Graphical Simulator for Teaching Microprogramming
tum era am2900 amd microprogramming teaching assembler simulator modular graphical eclipse plugin processor processor-architecture processor-simulator instruction-set-architecture emulator mograsim java emulation
Language:Java 12
mannasoumya / vm-go
Stack Based Virtual Machine in Golang
virtual-machine vm stack golang instruction-set-architecture instruction-set assembly-language stackbased-virtual-machine stackbased
Language:Go 11
Andpuv / lime-lab
LIME is an emulator of fantasy (digital) machines like those developed by community and non-community projects like fox32, OkamiStation, XrArch, Aphelion, doubleword, etc.
computer-simulator emulator low-level-programming simulator console-emulator instruction-set instruction-set-architecture instruction-set-simulator isa low-level-design
Language:C 10
david-palma / mips-32bit
Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.
vhdl mips 32-bit single-cycle multi-cycle computer-architecture hardware-description-language hardware-designs instruction-set-architecture isa mips32
Language:VHDL 8
MetaTransformers-Fractal-Workflow-System
angrysky56 / MetaTransformers-Fractal-Workflow-System
This repository contains the codebase for the MetaTransformers Fractal Workflow System, a comprehensive framework for managing and orchestrating complex workflows. The system is designed to handle a wide range of data types and workflows, from simple data processing to complex AI-driven transformations.
ai data-structures instruction-set-architecture llm node
Language:Python 6
arsalanyavari / mano-simulator
An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer
mano-simulator simulator 16-bit assembler compiler computer-architecture instruction-set-architecture cpp hardware-simulation mano-computer-simulator
Language:C++ 6
Mecca-Research / The-Binary-Decomposition-Interface
BDI - A proposed foundational computational substrate, a universal fabric designed to represent any computation.
assembly-language-programming instruction-set-architecture opcode-mnemonic syntax xbase cpp c python
Language:C 6
wisk / isabelle
Instruction Set Architecture Description Format
instruction-set-architecture
Language:Python 6
Didula98 / Building-a-Simple-Processor
Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL
alu cpu gtkwave instruction-set-architecture instructions verilog
Language:Verilog 5
RISC-Processor
Ecolash / RISC-Processor
𝗠𝗶𝗻𝗶𝗠𝗜𝗣𝗦 | 𝗥𝗜𝗦𝗖 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗼𝗿 𝗗𝗲𝘀𝗶𝗴𝗻 | CS39001 𝗖𝗼𝘂𝗿𝘀𝗲 𝗣𝗿𝗼𝗷𝗲𝗰𝘁
assembler assembly-language-programming computer-architecture controlpath datapath-design fpga-programming hardware-designs mips-architecture processor risc-architecture verilog-hdl vivado computer-organization-and-design control-unit instruction-set-architecture pipeline
Language:Verilog 5
hohaicongthuan / RV64IF
RISC-V 64-bit with 32-bit floating point extension support.
floating-point instruction-set-architecture risc-v verilog
Language:Verilog 5
IceWizard7 / frostbyte-cpu
Assembler, ISA & everything else featuring the 16-Bit Minecraft Redstone CPU "Frostybte"
assembler cpu cpu-architecture minecraft minecraft-schematics python cpu-simulator instruction-set-architecture redstone
Language:Python 5