instruction-set-architecture

There are 4 repositories under instruction-set-architecture topic.

hlorenzi / customasm
💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/
asm assembler assembly assembly-language bytecode bytecode-compiler compiler custom customizable instruction-set instruction-set-architecture machine-code microprocessor processor-architecture rust rust-lang user-defined virtual-machine vm webassembly
Language:Rust 719
Maratyszcza / Opcodes
Database of CPU Opcodes
instructions instruction-set-architecture x86 x86-64 opcodes
Language:Python 241
zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
simd processor verilog processor-design verilog-project multiplier adder instruction-set-architecture cadence-virtuoso cpu alu
Language:Verilog 125
gabrieldim / Assembly-MIPS-Instruction-Set
Assembly program with the MIPS instruction set
mips-assembly mips assembly assembly-language instruction-set-architecture
Language:Assembly 99
scarv / xcrypto
XCrypto: a cryptographic ISE for RISC-V
risc-v riscv verilog formal-verification yosys icarus-verilog hardware hardware-acceleration cryptography instruction-set-architecture open-source mit-license crypto cpu ise research-project xcrypto
Language:Verilog 92
edanor / umesimd
UME::SIMD A library for explicit simd vectorization.
avx simd scalar-types performance-tuning vectorization benchmark vector avx2 avx512 neon altivec instruction-set-architecture code-generation cpp cpp11 cpp14 cpp17 simd-instructions simd-programming ume
Language:C++ 90
mikeroyal / AMX-Guide
Advanced Matrix Extensions (AMX) Guide
advancedmatrixextensions amx cpu tilematrixset instruction-set-architecture accelerator datastreaming dsa fpga intel awesome awesome-list awesome-resources awesome-readme
Language:C++ 71
AluVM / rust-aluvm
Rust implementation of AluVM (RISC functional machine)
virtual-machine instruction-set-architecture edge-computing functional-programming embedded-systems risc microcontrollers smart-contracts blockchain rust
Language:Rust 59
riscv-assembler
kcelebi / riscv-assembler
RISC-V Assembly code assembler package for Python.
assembly-language-programming instruction-set-architecture python risc-v riscv-assembler
Language:Python 51
TomerAberbach / mano-simulator
🖥️ An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer.
mano hardware-simulator assembler mano-simulator mano-machine computer-architecture java java-8 java8 simulator javafx javafx-8 javafx-application java-application editor text-editor hardware-simulation 16bit architecture instruction-set-architecture
Language:Java 37
sjohann81 / hf-risc
HF-RISC SoC
mpsoc embedded-systems hf-risc processor soc computer-architecture risc-v mips instruction-set-architecture instruction-set-simulator
Language:C 29
alirezakay / RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
cpu cpu-model cpu-architecture processor-design processor-architecture mips-processor isa instruction-set-architecture multi-cycle risc-processor vhdl vhdl-code vhdl-modules
Language:VHDL 27
scarv / scarv-cpu
SCARV: a side-channel hardened RISC-V platform
riscv riscv32 xcrypto formal-verification yosys cryptography open-source mit-license crypto cpu ise instruction-set-architecture research-project verilator verilog
Language:Verilog 24
dmjio / LC3
:floppy_disk: The LC3 virtual machine
assembly haskell instruction-set-architecture lc3 opcodes virtual-machine
Language:Haskell 22
sdasgup3 / parallel-processor-design
Super scalar Processor design
verilog-hdl processor verilog processor-architecture processor-simulator instruction-set-architecture superscalar pipeline-processor pipeline-cpu assembler flex bison parallel-computing instruction-level-parallelism mnemonics forwarding bypassing branch-prediction instruction-set opcode
Language:Verilog 21
celebi-pkg / riscv-assembler
RISC-V Assembly code assembler package for Python.
assembler assembly instruction-set-architecture python risc-v riscv riscv-assembler
Language:Assembly 19
aphelion
orbit-systems / aphelion
64-bit RISC CPU Architecture
64-bit 64bit instruction-set instruction-set-architecture isa risc
19
katamaran-project / katamaran
Katamaran is a semi-automated separation logic verifier for the Sail specification language. It works on an embedded version of Sail called μSail and verifies separation logic-based contracts of functions by generating (succinct) first-order verification conditions.
instruction-set-architecture verification separation-logic symbolic-execution
Language:Coq 17
yonseicasl / Kite
Kite: Architecture Simulator for RISC-V Instruction Set
risc-v simulator architecture five-stage pipeline model education assembly computer-architecture microarchitecture pipelining branch-prediction cache instruction-set instruction-set-architecture memory instruction-dependency
Language:C++ 14
Mograsim
Mograsim-Team / Mograsim
Modular Graphical Simulator for Teaching Microprogramming
tum era am2900 amd microprogramming teaching assembler simulator modular graphical eclipse plugin processor processor-architecture processor-simulator instruction-set-architecture emulator mograsim java emulation
Language:Java 12
mannasoumya / vm-go
Stack Based Virtual Machine in Golang
virtual-machine vm stack golang instruction-set-architecture instruction-set assembly-language stackbased-virtual-machine stackbased
Language:Go 9
agicy / buptAsgmt-organization
北京邮电大学 2023-2024 春季学期《计算机组成原理》课程作业的相关文档
bus-system computer-organization cpu-organization instruction-set-architecture peripheral-devices storage-systems
7
arsalanyavari / mano-simulator
An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer
mano-simulator simulator 16-bit assembler compiler computer-architecture instruction-set-architecture cpp hardware-simulation mano-computer-simulator
Language:C++ 6
wisk / isabelle
Instruction Set Architecture Description Format
instruction-set-architecture
Language:Python 6
hohaicongthuan / RV64IF
RISC-V 64-bit with 32-bit floating point extension support.
floating-point instruction-set-architecture risc-v verilog
Language:Verilog 5
levindoneto / MIPS
Microprocessor without Interlocked Pipeline Stages with the extra JR, DIV and MFLO instructions implemented.
mips processor-architecture instruction-set-architecture monocycle-processor multicycle-processor pipeline-processor
5
player400 / pi
My very own CPU architecture! Emulator availible!
architecture assembly assembly-language computer-architecture cpp cpp-programming emulation emulator-development emulators hardware hardware-design instruction-set-architecture microcode
Language:C++ 5
Casparvolquardsen / Mikrorechner
Dieses Repository enthält die Implementierung eines RISC Prozessors mit VHDL, welche im Rahmen eines Projekts an der Universität Hamburg entstanden ist.
32-bit instruction-set-architecture microcomputer pipeline risc vhdl befehlssatz mikrocomputer
Language:VHDL 4
david-palma / mips-32bit
Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.
vhdl mips 32-bit single-cycle multi-cycle computer-architecture hardware-description-language hardware-designs instruction-set-architecture isa mips32
Language:VHDL 4
Didula98 / Building-a-Simple-Processor
Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL
alu cpu gtkwave instruction-set-architecture instructions verilog
Language:Verilog 4
farkoo / farkoo-Simulator
An assembler and hardware simulator for Mano Basic Computer, a 16-bit computer.
assembler compiler mano-computer-simulator hardware-simulation computer-architecture instruction-set-architecture 16-bit mano-simulator csharp
Language:C# 4
marceldobehere / goofy-cpu
a goofy 8 bit cpu
assembly-language cpu cpu-simulator csharp custom-cpu instruction-set-architecture logisim-computer logisim-evolution microcode
Language:C# 4
HarieshAnbalagan / RV32I
Minimalistic RV32I RISC-V Processor in System Verilog
processor risc-v rv32i computer-architecture digital-design fpga instruction-set-architecture simulations systemverilog
Language:SystemVerilog 3
lthoerner / smis
A project to create a basic instruction set for simple implementation and simple coding.
assembler assembly cpu-emulator disassembler instruction-set-architecture
Language:Rust 3
marceldobehere / MAAB-CPP-Interpreter
csharp custom-language instruction-set-architecture interpreter maal
Language:C++ 3
UserJHansen / Computer
Custom 32 bit computer
computer custom-computer-architecture instruction-set-architecture assembler cpu emulator assembly
Language:TypeScript 3