instruction-set-architecture

There are 4 repositories under instruction-set-architecture topic.

hlorenzi / customasm
💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/
assembly assembly-language assembler instruction-set instruction-set-architecture processor-architecture microprocessor bytecode bytecode-compiler compiler customizable custom virtual-machine vm machine-code webassembly user-defined asm rust rust-lang
Language:Rust 680
Maratyszcza / Opcodes
Database of CPU Opcodes
instructions instruction-set-architecture x86 x86-64 opcodes
Language:Python 238
zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
simd processor verilog processor-design verilog-project multiplier adder instruction-set-architecture cadence-virtuoso cpu alu
Language:Verilog 100
gabrieldim / Assembly-MIPS-Instruction-Set
Assembly program with the MIPS instruction set
mips-assembly mips assembly assembly-language instruction-set-architecture
Language:Assembly 98
edanor / umesimd
UME::SIMD A library for explicit simd vectorization.
avx simd scalar-types performance-tuning vectorization benchmark vector avx2 avx512 neon altivec instruction-set-architecture code-generation cpp cpp11 cpp14 cpp17 simd-instructions simd-programming ume
Language:C++ 89
scarv / xcrypto
XCrypto: a cryptographic ISE for RISC-V
risc-v riscv verilog formal-verification yosys icarus-verilog hardware hardware-acceleration cryptography instruction-set-architecture open-source mit-license crypto cpu ise research-project xcrypto
Language:Verilog 86
AluVM / rust-aluvm
Rust implementation of AluVM (RISC functional machine)
blockchain edge-computing embedded-systems functional-programming instruction-set-architecture microcontrollers risc rust smart-contracts virtual-machine
Language:Rust 57
mikeroyal / AMX-Guide
Advanced Matrix Extensions (AMX) Guide
advancedmatrixextensions amx cpu tilematrixset instruction-set-architecture accelerator datastreaming dsa fpga intel awesome awesome-list awesome-resources awesome-readme
Language:C++ 51
riscv-assembler
kcelebi / riscv-assembler
RISC-V Assembly code assembler package for Python.
assembly-language-programming instruction-set-architecture python risc-v riscv-assembler
Language:Python 47
TomerAberbach / mano-simulator
🖥️ An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer.
mano hardware-simulator assembler mano-simulator mano-machine computer-architecture java java-8 java8 simulator javafx javafx-8 javafx-application java-application editor text-editor hardware-simulation 16bit architecture instruction-set-architecture
Language:Java 35
sjohann81 / hf-risc
HF-RISC SoC
mpsoc embedded-systems hf-risc processor soc computer-architecture risc-v mips instruction-set-architecture instruction-set-simulator
Language:C 27
alirezakay / RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
cpu cpu-model cpu-architecture processor-design processor-architecture mips-processor isa instruction-set-architecture multi-cycle risc-processor vhdl vhdl-code vhdl-modules
Language:VHDL 26
scarv / scarv-cpu
SCARV: a side-channel hardened RISC-V platform
cpu crypto cryptography formal-verification instruction-set-architecture ise mit-license open-source research-project riscv riscv32 verilator verilog xcrypto yosys
Language:Verilog 22
dmjio / LC3
:floppy_disk: The LC3 virtual machine
assembly haskell instruction-set-architecture lc3 opcodes virtual-machine
Language:Haskell 20
sdasgup3 / parallel-processor-design
Super scalar Processor design
verilog-hdl processor verilog processor-architecture processor-simulator instruction-set-architecture superscalar pipeline-processor pipeline-cpu assembler flex bison parallel-computing instruction-level-parallelism mnemonics forwarding bypassing branch-prediction instruction-set opcode
Language:Verilog 20
katamaran-project / katamaran
Katamaran is a semi-automated separation logic verifier for the Sail specification language. It works on an embedded version of Sail called μSail and verifies separation logic-based contracts of functions by generating (succinct) first-order verification conditions.
instruction-set-architecture verification separation-logic symbolic-execution
Language:Coq 16
celebi-pkg / riscv-assembler
RISC-V Assembly code assembler package for Python.
assembler assembly instruction-set-architecture python risc-v riscv riscv-assembler
Language:Assembly 14
Mograsim
Mograsim-Team / Mograsim
Modular Graphical Simulator for Teaching Microprogramming
tum era am2900 amd microprogramming teaching assembler simulator modular graphical eclipse plugin processor processor-architecture processor-simulator instruction-set-architecture emulator mograsim java emulation
Language:Java 13
aphelion
orbit-systems / aphelion
64-bit RISC CPU Architecture
instruction-set-architecture isa 64-bit 64bit instruction-set risc
13
yonseicasl / Kite
Kite: Architecture Simulator for RISC-V Instruction Set
risc-v simulator architecture five-stage pipeline model education assembly computer-architecture microarchitecture pipelining branch-prediction cache instruction-set instruction-set-architecture memory instruction-dependency
Language:C++ 13
mannasoumya / vm-go
Stack Based Virtual Machine in Golang
virtual-machine vm stack golang instruction-set-architecture instruction-set assembly-language stackbased-virtual-machine stackbased
Language:Go 7
wisk / isabelle
Instruction Set Architecture Description Format
instruction-set-architecture
Language:Python 6
arsalanyavari / mano-simulator
An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer
mano-simulator simulator 16-bit assembler compiler computer-architecture instruction-set-architecture cpp hardware-simulation mano-computer-simulator
Language:C++ 5
levindoneto / MIPS
Microprocessor without Interlocked Pipeline Stages with the extra JR, DIV and MFLO instructions implemented.
mips processor-architecture instruction-set-architecture monocycle-processor multicycle-processor pipeline-processor
5
Casparvolquardsen / Mikrorechner
Dieses Repository enthält die Implementierung eines RISC Prozessors mit VHDL, welche im Rahmen eines Projekts an der Universität Hamburg entstanden ist.
32-bit instruction-set-architecture microcomputer pipeline risc vhdl befehlssatz mikrocomputer
Language:VHDL 4
Didula98 / Building-a-Simple-Processor
Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL
alu cpu gtkwave instruction-set-architecture instructions verilog
Language:Verilog 4
farkoo / farkoo-Simulator
An assembler and hardware simulator for Mano Basic Computer, a 16-bit computer.
assembler compiler mano-computer-simulator hardware-simulation computer-architecture instruction-set-architecture 16-bit mano-simulator csharp
Language:C# 4
fgmn / Computer-Organization-Course-Design
SDU 20级计科计组课设
computer-compose-principle course-design cpu-design instruction-set-architecture
Language:VHDL 4
hohaicongthuan / RV64IF
RISC-V 64-bit with 32-bit floating point extension support.
floating-point instruction-set-architecture risc-v verilog
Language:Verilog 4
hvudeshi / Context-Switching
Multi-Threaded Simulation of Process Switching in Operating System.
operating-system c threading multi-threading process-scheduler process-simulator instruction-set-architecture
Language:C 3
jamestiotio / compstruct
SUTD 2020 50.002 Computation Structures Code Dump
computation-structures hardware instruction-set-architecture computer-architecture instruction-set netlist turing-machine netlist-simulator turing-machine-simulator beta risc digital-systems lucid fpga hardware-description-language cpu os central-processing-unit operating-system
Language:C 3
riscal-cpu
Psmths / riscal-cpu
RISCAL is a 32-bit reduced instruction-set computer (RISC) designed for learning and research purposes. It is named after my dog, Rascal.
virtual-machine instruction-set-architecture assembly risc machine-code assembler obfuscation virtualization
Language:C++ 3
Sacusa / MoCha
A pedagogical processor on FPGA, developed at NIIT University.
fpga vhdl microprocessor processor cpu educational vlsi computer-architecture microarchitecture architectural-simulation assembler cycle-accurate bootloader assembly-language spi-flash bit-banging stepper-motor-driver synthesis instruction-set-architecture
Language:VHDL 3
Danila-Pechenev / InstructionAnalysisFramework
Framework for collecting and analyzing data on the use of machine instructions
analysis gnu-linux instruction-set-architecture instructions linux risc-v linux-distributions x86-64 x86-assembly framework tool code-analysis code-analysis-tool
Language:Jupyter Notebook 2
JohnMachado11 / CS104-Computer-Architecture
Python implementation of a 32-bit processor with its own ISA (Instruction Set Architecture)
32bit binary computer-science instruction-set-architecture python
Language:Python 2
lthoerner / smis
A project to create a basic instruction set for simple implementation and simple coding.
assembler assembly cpu-emulator disassembler instruction-set-architecture
Language:C 2