vector-processor

There are 0 repository under vector-processor topic.

ProjectPhysX / OpenCL-Wrapper
OpenCL is the most powerful programming language ever created. Yet the OpenCL C++ bindings are cumbersome and the code overhead prevents many people from getting started. I created this lightweight OpenCL-Wrapper to greatly simplify OpenCL software development with C++ while keeping functionality and performance.
gpu gpu-acceleration gpu-computing gpu-programming opencl gpgpu gpgpu-computing vector-processor vectorization
Language:C++ 442
vproc / vicuna
RISC-V Zve32x Vector Coprocessor
risc-v vector-processor coprocessor systemverilog
Language:Assembly 192
ic-lab-duth / RISC-V-Vector
Vector processor for RISC-V vector ISA
vector-processor riscv risc-v systemverilog
Language:SystemVerilog 130
stillwater-sc / RISC-V-TensorCore
Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
vector-processor reproducible-computation risc-v64
Language:Verilog 57
klessydra / T13x
An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
klessydra t13x t03x t02x riscv pulpino superscalar vector-processor accelerator simd mimd
Language:VHDL 45
timurkelin / simsimd
Development and simulation framework for Application Specific Vector Processor
simd single-instruction-multiple-data asip application-specific architecture vector-processor cycle-accurate data-driven system-simulation systemc model-based dsp digital-signal-processing vector-core network-on-chip heterogeneous-structure heterogeneous-computing system-level-simulation multimode-processing simulation-framework
Language:C++ 16
sarthi92 / vector_processor
Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor
verilog cpu-design vector-processor memory
Language:Verilog 10
Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.
bluespec bluespec-systemverilog bluespec-systemverilog-language processor-design processor-architecture vector-processor ram bus hardware hardware-designs hardware-acceleration processor vlsi-cad vlsi vlsi-physical-design vlsi-design
Language:Bluespec 7
rumlenordstroem / penta-five
A RISC-V vector processor written in Chisel HDL.
chisel fpga processor risc-v vector-processor
Language:Scala 4
ce-box / CE4302-vector-processor
Vector ASIP for the application of filters to an image 🖼️
computer-architecture fpga pipelined-processors vector-processor vhdl
Language:SystemVerilog 1

vector-processor

ProjectPhysX / OpenCL-Wrapper

vproc / vicuna

ic-lab-duth / RISC-V-Vector

stillwater-sc / RISC-V-TensorCore

klessydra / T13x

timurkelin / simsimd

sarthi92 / vector_processor

Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

rumlenordstroem / penta-five

ce-box / CE4302-vector-processor