Yosys Headquarters (YosysHQ)

Yosys Headquarters

YosysHQ

Organization data from Github https://github.com/YosysHQ

Yosys Open SYnthesis Suite

Home Page:http://yosyshq.net/

GitHub:@YosysHQ

Yosys Headquarters's repositories

yosys

Yosys Open SYnthesis Suite

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

Language:VerilogLicense:ISCStargazers:3763Issues:170Issues:186

nextpnr

nextpnr portable FPGA place and route tool

Language:C++License:ISCStargazers:1546Issues:68Issues:481

oss-cad-suite-build

Multi-platform nightly builds of open source digital design and verification tools

Language:ShellLicense:ISCStargazers:1223Issues:26Issues:137

icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Language:PythonLicense:ISCStargazers:1102Issues:68Issues:143

apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

Language:VerilogLicense:MITStargazers:595Issues:37Issues:109

sby

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

Language:PythonLicense:NOASSERTIONStargazers:479Issues:32Issues:146

prjtrellis

Documenting the Lattice ECP5 bit-stream format.

Language:PythonLicense:NOASSERTIONStargazers:431Issues:32Issues:80

riscv-formal

RISC-V Formal Verification Framework

Language:VerilogLicense:ISCStargazers:164Issues:13Issues:19

nerv

Naive Educational RISC V processor

Language:SystemVerilogLicense:NOASSERTIONStargazers:88Issues:11Issues:3

mcy

Mutation Cover with Yosys (MCY)

Language:C++License:ISCStargazers:87Issues:14Issues:6

eqy

Equivalence checking with Yosys

Language:C++License:NOASSERTIONStargazers:46Issues:7Issues:28

VlogHammer

A Verilog Synthesis Regression Test

Language:ShellStargazers:37Issues:7Issues:0

abc

ABC: System for Sequential Logic Synthesis and Formal Verification

Language:CLicense:NOASSERTIONStargazers:29Issues:6Issues:0

padring

A padring generator for ASICs

Language:C++License:ISCStargazers:25Issues:8Issues:7

prjpeppercorn

Project Peppercorn - GateMate FPGA Bitstream Documentation

Language:PythonLicense:ISCStargazers:25Issues:10Issues:0

sby-gui

GUI for SymbiYosys

Language:C++License:ISCStargazers:17Issues:7Issues:19

setup-oss-cad-suite

Set up your GitHub Actions workflow with a OSS CAD Suite

Language:TypeScriptLicense:ISCStargazers:16Issues:8Issues:5

prjtrellis-db

Project Trellis database

License:CC0-1.0Stargazers:13Issues:7Issues:0

imctk

Incremental Model Checking Toolkit

Language:RustLicense:NOASSERTIONStargazers:10Issues:8Issues:44

prjpeppercorn-test-cases

Project Peppercorn GateMate Test Cases

Language:VerilogLicense:ISCStargazers:10Issues:0Issues:0

rtlil-mlir

Yosys RTLIL dialect for MLIR

Language:C++License:ISCStargazers:10Issues:0Issues:0

scy

Sequence of Covers with Yosys

Language:SystemVerilogLicense:NOASSERTIONStargazers:6Issues:11Issues:3

mau

Modular Application Utilities

Language:PythonLicense:ISCStargazers:5Issues:12Issues:1

yosyshq.github.io

www.yosyshq.net

Language:HTMLStargazers:4Issues:7Issues:0

yosys-web

Yosys Web Page

furo-ys

A clean customizable documentation theme for Sphinx

Language:SassLicense:MITStargazers:1Issues:0Issues:0

yosys-manual-build

Yosys manual

Language:DockerfileStargazers:1Issues:8Issues:0
Stargazers:0Issues:7Issues:0