cocotb

There are 3 repositories under cocotb topic.

apfelaudio / eurorack-pmod
A eurorack-friendly audio frontend compatible with many FPGA boards.
cocotb electronics eurorack fpga hardware kicad modular-synthesizers pmod synthesizer verilog yosys
Language:SystemVerilog 161
fvutils / pyvsc
Python packages providing a library for Verification Stimulus and Coverage
cocotb constrained-random constraints coverage functional-coverage python random-stimulus randomization verification-stimulus
Language:Python 105
mciepluc / cocotb-coverage
Functional Coverage and Constrained Randomization Extensions for Cocotb
cocotb mdv verification hdl
Language:Python 100
cocotb / cocotb-bus
Pre-packaged testbenching tools and reusable bus interfaces for cocotb
testbench bus interface hdl verilog vhdl cocotb
Language:Python 46
ttchisholm / 10g-low-latency-ethernet
10G Low Latency Ethernet
cocotb ethernet fpga pyuvm systemverilog xilinx
Language:SystemVerilog 26
themperek / cocotb-vivado
Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
cocotb python simulation verification vivado xilinx
Language:Python 24
Elphel / vdt-plugin
mirror of https://git.elphel.com/Elphel/vdt-plugin
verilog eclipse ide vivado quartus icarus-verilog cocotb gtkwave eclipse-plugin
Language:Java 15
intel / rohd-cosim
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
co-simulation cocotb cosim cosimulation dart framework hardware hardware-design hardware-verification python rohd rtl simulator rohd-vf
Language:Dart 14
andreaskuster / black-parrot-branch-predictor
Branch Predictor Optimization for BlackParrot
branch branch-predictors vlsi ci continuous-integration cocotb black-parrot cbp-5 always-taken bimodal gselect gshare perceptron tournament two-level-local trace cocotb-testing co-simulation
Language:HTML 13
aignacio / cocotbext-ahb
Cocotb AHB Extension - AHB VIP
ahb cocotb cocotbext vip
Language:Python 7
chuckb / ghdl-interactive-sim
Interactive GHDL simulation of a VHDL adder using Python, Cocotb, and pygame
cocotb ghdl gui pygame python simulator vhdl vpi
Language:Python 6
teobiton / cryptopen
Library of hardware accelerators for popular cryptographic hash functions in SystemVerilog
algorithm cocotb cryptography systemverilog hardware accelerator asic fpga
Language:Python 4
mcejp / Poly94
Yet another faux-retro game system
ulx3s vexriscv yosys fpga prjtrellis cocotb
Language:Verilog 2
pwiecha / yas_router
Yet Another Simple Router - a COCOTB verification of the Verilog RTL model example
cocotb python python3 verilog router rtl tutorial
Language:Verilog 2
rafaelnp / fpga_dev_docker
Docker image for fpga development
fpga docker verification ghdl ghdl-yosys-plugin cocotb
Language:Dockerfile 2
rj45 / rjsc5
rjsc5 a 16-bit RISC-V CPU
cocotb cpu risc-v verilog
Language:Assembly 2
2uger / verilog_uart_hw
Verilog UART implementation with Vivado build scripts to test loopback on Xilinx Arty board
cocotb uart verilog fpga hardware uart-verilog xilinx-fpga
Language:Verilog 1
angeliaplutus / ipcoredesign
Design & Verification of IP Cores and ICs, Artificial Intelligence
design-of-ip-cores-and-ics verification artificial-intelligence cocotb hardware-designs osvvm uvm uvvm
Language:VHDL 1
complexexponentials / lms-equalizer
LMS equalizer implemented in RTL
verilog lms cocotb
Language:VHDL 1
npatsiatzis / recirculation_mux
cocotb pyuvm vhdl systemverilog uvm verilator
Language:Python 1
npatsiatzis / uart
cocotb pyuvm vhdl systemverilog uvm verilator
Language:VHDL 1
RDSik / FPGA_transceiver
modelsim vivado python cocotb hdlmake testbench icarus-verilog verilog-hdl
Language:Verilog 1
ShwetaKiranTotla / Micro-processor-Design-Verification
Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.
cocotb cocotb-testing design-verification flash makefile python risc sdram sdram-controller testbench uart verification
Language:Verilog 1
vacagonzalo / soc-workflow-vhdl
Example workflow project for VHDL development.
axi axi-bus cocotb cocotb-testing tcl tcl-scripts vhdl vivado workflow
Language:VHDL 1
xiajenny / missing-module-cocotb-example
Simulate incomplete verilog module with python
verilog cocotb python testbench
Language:Python 1
yasin-peker / Verilog-HDL-Based-Car-Parking-System-FPGA
This repository contains the Verilog HDL implementation of a Car Parking System running on an FPGA. The system is designed to manage car entry and exit through two sensors located at the entrance and exit of the car park. It allows registered users to enter the car park by entering their passwords and controls the traffic lights accordingly.
cocotb fpga makefile verilog
Language:Python 1
167rgc911 / hdl_study
mostly simple VHDL stuff
cocotb ghdl vhdl
0
npatsiatzis / bcd_bin_conv
cocotb pyuvm vhdl
Language:Python 0
npatsiatzis / cdc_handshake
cocotb vhdl systemverilog pyuvm uvm verilator
Language:Python 0
npatsiatzis / fifo_asynchronous
cocotb pyuvm vhdl systemverilog uvm verilator
Language:Python 0
EngCake / icarus-verilog
Quick starter project for using Icarus Verilog + Cocotb
cocotb cocotb-testing starter-project template template-project verilog verilog-hdl
Language:Python
npatsiatzis / fir
cocotb pyuvm systemverilog vhdl sby verilator
Language:Python
npatsiatzis / gray_bin_conv
cocotb pyuvm vhdl
Language:Python
npatsiatzis / moving_average
cocotb pyuvm systemverilog vhdl verilator
Language:Python
npatsiatzis / VGA
cocotb vhdl systemverilog verilator
Language:SystemVerilog
RDSik / i2c_master
hdlmake verilog-hdl cocotb icarus-verilog modelsim vivado testbench
Language:Verilog

cocotb

apfelaudio / eurorack-pmod

fvutils / pyvsc

mciepluc / cocotb-coverage

cocotb / cocotb-bus

ttchisholm / 10g-low-latency-ethernet

themperek / cocotb-vivado

Elphel / vdt-plugin

intel / rohd-cosim

andreaskuster / black-parrot-branch-predictor

aignacio / cocotbext-ahb

chuckb / ghdl-interactive-sim

teobiton / cryptopen

mcejp / Poly94

pwiecha / yas_router

rafaelnp / fpga_dev_docker

rj45 / rjsc5

2uger / verilog_uart_hw

angeliaplutus / ipcoredesign

complexexponentials / lms-equalizer

npatsiatzis / recirculation_mux

npatsiatzis / uart

RDSik / FPGA_transceiver

ShwetaKiranTotla / Micro-processor-Design-Verification

vacagonzalo / soc-workflow-vhdl

xiajenny / missing-module-cocotb-example

yasin-peker / Verilog-HDL-Based-Car-Parking-System-FPGA

167rgc911 / hdl_study

npatsiatzis / bcd_bin_conv

npatsiatzis / cdc_handshake

npatsiatzis / fifo_asynchronous

EngCake / icarus-verilog

npatsiatzis / fir

npatsiatzis / gray_bin_conv

npatsiatzis / moving_average

npatsiatzis / VGA

RDSik / i2c_master