cocotb

There are 3 repositories under cocotb topic.

chili-chips-ba / wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
cocotb embedded fpga iss risc-v rtl verilator verilog vpn wireguard vproc
Language:Verilog 1250
0BAB1 / HOLY_CORE_COURSE
Learn how to build our own RV32I core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial with schemes & explanation.
cocotb fpga hardware learning open-source riscv verilog
Language:Python 251
apfaudio / eurorack-pmod
A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.
electronics eurorack fpga hardware modular-synthesizers cocotb kicad synthesizer verilog yosys pmod
Language:SystemVerilog 221
fvutils / pyvsc
Python packages providing a library for Verification Stimulus and Coverage
verification-stimulus coverage constraints random-stimulus functional-coverage constrained-random cocotb randomization python
Language:Python 129
mciepluc / cocotb-coverage
Functional Coverage and Constrained Randomization Extensions for Cocotb
cocotb hdl mdv verification
Language:Python 117
cocotb / cocotb-bus
Pre-packaged testbenching tools and reusable bus interfaces for cocotb
bus cocotb hdl interface testbench verilog vhdl
Language:Python 70
ttchisholm / 10g-low-latency-ethernet
10G Low Latency Ethernet
cocotb ethernet fpga pyuvm systemverilog xilinx
Language:SystemVerilog 59
Weiyet / RTLStructLib
RTL data structure
cocotb data-structures rtl system-verilog uvm-verification verilog-hdl
Language:SystemVerilog 52
themperek / cocotb-vivado
Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
cocotb python simulation verification vivado xilinx
Language:Python 46
intel / rohd-cosim
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
co-simulation cocotb cosim cosimulation dart framework hardware hardware-design hardware-verification python rohd rtl simulator rohd-vf
Language:Dart 24
hurisson / pyuvm_primer
Examples for using pyuvm
apb3 cocotb python pyuvm
Language:Python 19
aignacio / cocotbext-ahb
Cocotb AHB Extension - AHB VIP
ahb cocotb vip cocotbext
Language:Python 16
andreaskuster / black-parrot-branch-predictor
Branch Predictor Optimization for BlackParrot
branch branch-predictors vlsi ci continuous-integration cocotb black-parrot cbp-5 always-taken bimodal gselect gshare perceptron tournament two-level-local trace cocotb-testing co-simulation
Language:HTML 15
Elphel / vdt-plugin
mirror of https://git.elphel.com/Elphel/vdt-plugin
verilog eclipse ide vivado quartus icarus-verilog cocotb gtkwave eclipse-plugin
Language:Java 15
psychogenic / microcotb
micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop
cocotb hardware-in-the-loop testbench vcd verification
Language:Python 15
chuckb / ghdl-interactive-sim
Interactive GHDL simulation of a VHDL adder using Python, Cocotb, and pygame
python ghdl cocotb vpi pygame simulator vhdl gui
Language:Python 9
mmichilot / cocotb_kernel
A cocotb kernel for Jupyter
cocotb jupyter verification
Language:Python 8
merledu / coco-rvtb
Generic testbench for RISC-V CPUs
cocotb pyuvm riscv uvm
Language:Python 7
JitheshVijay / cocotbext-qspi
Cocotb extension for QSPI verification
cocotb cocotbext interface vip
Language:Python 6
ShwetaKiranTotla / Micro-processor-Design-Verification
Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.
cocotb cocotb-testing design-verification flash makefile python risc sdram sdram-controller testbench uart verification
Language:Verilog 6
mcejp / Poly94
Yet another faux-retro game system
cocotb fpga prjtrellis ulx3s vexriscv yosys
Language:Verilog 5
ktbarrett / coconext
Staging area for new features of cocotb
cocotb eda hdl python verification
Language:Python 4
pwiecha / yas_router
Yet Another Simple Router - a COCOTB verification of the Verilog RTL model example
cocotb python python3 verilog router rtl tutorial
Language:Verilog 4
RDSik / verilog-transceiver
Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit
modelsim vivado python cocotb hdlmake icarus-verilog make chocolatey winget verilog fpga testbench docker
Language:Verilog 4
teobiton / cryptopen
Library of hardware accelerators for popular cryptographic hash functions in SystemVerilog
algorithm cocotb cryptography systemverilog hardware accelerator asic fpga
Language:Python 4
amutioalex / cocoman
Regression runner for cocotb-based verification workflows.
cocotb python regression testbench verification
Language:Python 3
complexexponentials / lms-equalizer
LMS equalizer implemented in RTL
verilog lms cocotb
Language:VHDL 3
rz-jenc
raumzeitt / rz-jenc
JPEG encoder IP core(s) written in Verilog.
cocotb encoder fpga jpeg verilog
Language:SystemVerilog 3
rj45 / rjsc5
rjsc5 a 16-bit RISC-V CPU
cocotb cpu risc-v verilog
Language:Assembly 3
npatsiatzis / fifo_asynchronous
cocotb pyuvm vhdl systemverilog uvm verilator
Language:Python 2
opendv360 / verification-diagrams
This collection of verification diagrams is created to help educators, students, and engineers visualize complex hardware verification concepts. These illustrations transform complex concepts into understandable visuals.
design design-verification systemverilog uvm uvm-component uvm-verification verification opendv cocotb hdl verilog vhdl wavechip
2
rafaelnp / fpga_dev_docker
Docker image for fpga development
fpga docker verification ghdl ghdl-yosys-plugin cocotb
Language:Dockerfile 2
bjohnsonfl / aes
Python AES
aes aes256-cbc block-cipher cocotb cosimulation cryptography decryption encryption hdl pytest python systemverilog testbench verilator vhdl
Language:Python 1
ERAS-Research / caveat
Framework for Context-Aware Verification, Emulation, and Training
cocotb education fpga verification
Language:Python 1
RDSik / si5340-config-loader
Module for load configuration from ClockBuilderPro to Si5340 PLL via i2c interface
chocolatey cocotb fpga hdlmake i2c make makefile modelsim quartus systemverilog testbench verilator verilog winget
Language:Verilog 1
WAVECHIP / cocotb-tutorial
Getting started with cocotb
cocotb gtkwave icarus-verilog python systemverilog verification verilog opendv wavechip
Language:Python 1

cocotb

chili-chips-ba / wireguard-fpga

0BAB1 / HOLY_CORE_COURSE

apfaudio / eurorack-pmod

fvutils / pyvsc

mciepluc / cocotb-coverage

cocotb / cocotb-bus

ttchisholm / 10g-low-latency-ethernet

Weiyet / RTLStructLib

themperek / cocotb-vivado

intel / rohd-cosim

hurisson / pyuvm_primer

aignacio / cocotbext-ahb

andreaskuster / black-parrot-branch-predictor

Elphel / vdt-plugin

psychogenic / microcotb

chuckb / ghdl-interactive-sim

mmichilot / cocotb_kernel

merledu / coco-rvtb

JitheshVijay / cocotbext-qspi

ShwetaKiranTotla / Micro-processor-Design-Verification

mcejp / Poly94

ktbarrett / coconext

pwiecha / yas_router

RDSik / verilog-transceiver

teobiton / cryptopen

amutioalex / cocoman

complexexponentials / lms-equalizer

raumzeitt / rz-jenc

rj45 / rjsc5

npatsiatzis / fifo_asynchronous

opendv360 / verification-diagrams

rafaelnp / fpga_dev_docker

bjohnsonfl / aes

ERAS-Research / caveat

RDSik / si5340-config-loader

WAVECHIP / cocotb-tutorial