There are 1 repository under basys3 topic.
Image Processing Toolbox in Verilog using Basys3 FPGA
⚙Hardware Synthesis Laboratory Using Verilog
A Single Cycle Risc-V 32 bit CPU
A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
Single Cycle 32 bit MIPS
👻 Simple Undertale-like game on Basys3 FPGA written in Verilog
This repository has basic examples in VHDL using Basys3 board.
CS4362 - Hardware Description Languages. Implemented SNN on an FPGA for real-time image processing using VHDL
Pulse generator on Basys 3 FPGA board
Morse Code Encoder on Basys 3 [Artix-7, part: xc7a35tcpg236-1]
Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.
FPGA Audio Effect System project for Electronic Engineering course. This project spanned two semesters and was my final year project
Digital clock implemented in vhdl for the Basys 3 Board from Digilent.
Color Detection using Basys3 FPGA
This is the repo is created for helping fellow Bilkenteers to pass their EEE102 Digital Electronics course. You can find Lab answers from Lab 1 to Final Project! Have fun!
FPGA Implementation of Full Search Block matching using an asynchronous handshake based FSM.
A Sound and Sight Entertainment System (SSES) implemented on Basys3 FPGA Board
Digital Clock for the Basys 3 FPGA
This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.
Basys 3 driver for a Raspberry Pi NoIR 2.1 camera - COMPE470L class project
Complex Adder with Seven Segment Display
Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..
Extremely basic countdown clock project for the Basys 3 FPGA development board.
Term project for CS223 Digital - Design course.
Marble maze game implemented on SystemVerilog for Basys3
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
Magellan - A HW monitor/debugger for Basys 3
This is a fruit catching arcade style game made entirely with verilog. It is implemented on the Basys3 FPGA board and has gamecube controller support.
Minimalist 8 bit multicycle RISC CPU
Displaying images taken from an OV7670/laptop camera
An cellular automata game for a 8x8 matrix on the BetiBoard. (requires Basys3 board)
A Nanoprocessor designed to run on the Basys3 FPGA desgined using Xlinx Vivado with VHD using Registers, Add/Sub Unit, Decoders, Multiplexers which have been implemented seperately.