basys3

There are 1 repository under basys3 topic.

Gowtham1729 / Image-Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
verilog verilog-hdl verilog-project vhdl python3 basys3 basys-board basys fpga pixel convolution hsync basys3-fpga motion-blur ram python coe vivado image-processing digital-systems
Language:VHDL 163
tongplw / HW-Syn-Lab
⚙Hardware Synthesis Laboratory Using Verilog
verilog vivado xilinx basys3 hardware hardware-synthesis uart vga
Language:Verilog 37
Handwritten-Digit-Recognition-Painter
j3soon / Handwritten-Digit-Recognition-Painter
A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.
artix-7 basys3 deep-learning hardware painter verilog
Language:VHDL 23
martinKindall / risc-v-single-cycle
A Single Cycle Risc-V 32 bit CPU
basys3 basys3-fpga riscv riscv-assembly riscv32 rv32i single-cycle-processor systemverilog
Language:SystemVerilog 21
tongplw / Undertale-Verilog
👻 Simple Undertale-like game on Basys3 FPGA written in Verilog
undertale basys3 basys3-fpga verilog verilog-project fpga fpga-game fpga-board vga uart
Language:Verilog 16
CynicalApe / BASYS3-PONG
BASYS 3 - PONG GAME
basys3 verilog vhdl basys-board pong-game
Language:SystemVerilog 13
chili-chips-ba / openXC7-TetriSaraj
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
basys3 fpga gamedev nextpnr open-source rtl tetris-game verilog-hdl xc7a35t xilinx yosys soc
Language:Verilog 10
martinKindall / mips_cpu
Single Cycle 32 bit MIPS
fpga mips single-cycle systemverilog basys3 basys3-fpga mips-cpu single-cycle-processor
Language:SystemVerilog 10
bilalkabas / Basys3-VHDL-Basics
This repository has basic examples in VHDL using Basys3 board.
vhdl-examples basys3 fpga-programming vivado
Language:VHDL 8
raleighlittles / Applied_Digital_Logic_Exercises_Using_FPGAs
Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.
fpga microblaze-mcs basys3 artix-7 applied-digital-logic-exercises vivado verilog hdl
Language:Verilog 8
soundjuice / Basys3-Pulse-Generator
Pulse generator on Basys 3 FPGA board
vhdl fpga pulse-generator basys3
Language:VHDL 8
Maneesh3 / Morse_Code_Encoder_Basys3
Morse Code Encoder on Basys 3 [Artix-7, part: xc7a35tcpg236-1]
basys3 morse
Language:Verilog 6
romybompart / Basys3-clock-alarm-with-buzzer
Digital clock implemented in vhdl for the Basys 3 Board from Digilent.
vhd vhdl-code digilent basys3 basys3-fpga digital-clock clock digit basys3-clock-alarm buzzer buzzer-termination
Language:VHDL 6
antimattercorrade / Color_Detection_BASYS3
Color Detection using Basys3 FPGA
vhdl verilog color-detection basys3 fpga
Language:VHDL 5
CankutBoraTuncer / Bilkent-EEE102-Labs
This is the repo is created for helping fellow Bilkenteers to pass their EEE102 Digital Electronics course. You can find Lab answers from Lab 1 to Final Project! Have fun!
eee102 vhdl labs bilkent digitalelectronics basys3
5
meiniKi / logIP
Logic Analyzer IP Core
asic basys3 digital formal-verification fpga ip logicanalyzer measurements sump systemverilog verilog hardware-description-language hdl ols amd vivado xilinx logip symbiyosys
Language:SystemVerilog 5
ColtonBeery / Digital_Clock
Digital Clock for the Basys 3 FPGA
basys-3 basys3-fpga basys3 digital-clock verilog verilog-hdl
Language:Verilog 4
DeanDev94 / FPGA-Audio-Effects-System
FPGA Audio Effect System project for Electronic Engineering course. This project spanned two semesters and was my final year project
fpga basys3 verilog xilinx vivado audio-processing audio-effects cork-institute-of-technology
Language:Verilog 4
Prajjv / RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg
Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..
7-segment artix-7 basys3 basys3-fpga basys3-fpga-board fibonacci-numbers fibonacci-sequence microprocessor risc-v single-cycle-processor verilog vivado vivado-hls
Language:Tcl 4
vinayak1998 / Reflex-Tester
This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.
xilinx xilinx-fpga hand-eye-coordination xilinx-vivado vhdl lfsr xilinx-ise fpga basys3 vivado architecture
Language:VHDL 4
aliasgharchakera / flappy-bird
The game of flappy bird coded in Verilog
basys3 fpga verilog
Language:HTML 3
bingsen0806 / EE2026
A Sound and Sight Entertainment System (SSES) implemented on Basys3 FPGA Board
basys3 basys3-fpga verilog vivado pixel-art
Language:Verilog 3
ColtonBeery / Basys3_Camera_Driver
Basys 3 driver for a Raspberry Pi NoIR 2.1 camera - COMPE470L class project
basys3 basys3-fpga basys-3 fpga verilog camera vga vga-driver
Language:Verilog 3
neelabhro / Complex-Adder-with-SSD
Complex Adder with Seven Segment Display
fpga basys3 fsm finite-state-machine seven-segments-display adder
Language:Verilog 3
praveenVnktsh / Hardware-Accelerated-Motion-Estimation-using-FSBM-and-FPGA
FPGA Implementation of Full Search Block matching using an asynchronous handshake based FSM.
vga coe macroblock bram pixels verilog-hdl fpga basys3 basys3-fpga python vhdl hdl motion estimation motion-estimation
Language:VHDL 3
raleighlittles / Basys3CountdownClock
Extremely basic countdown clock project for the Basys 3 FPGA development board.
verilog hdl xilinx vivado xdc seven-segment-display fpga basys-3 basys3
Language:Verilog 3
segocago / CS223-Digital-Design-Highway-Racing
Term project for CS223 Digital - Design course.
bilkent-university systemverilog digital-design basys3 dotmatrix fpga
Language:SystemVerilog 3
yalchinAlv / MarbleMazeGame
Marble maze game implemented on SystemVerilog for Basys3
systemverilog basys3 mpu6050 max7219
Language:SystemVerilog 3
aryan-programmer / axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
artix artix-7 basys3 fpga vitis vivado xilinx xilinx-fpga axi axi-lite axi-memory-mapped axi-stream embedded hls vitis-hls vivado-ip-integrator vivado-vitis xilinx-hls xilinx-vitis xilinx-vivado
Language:TeX 2
chclau / basys3_Magellan
Magellan - A HW monitor/debugger for Basys 3
basys3 basys3-fpga basys3-fpga-board vhdl vhdl-code vhdl-examples
Language:VHDL 2
MaxwellSiyuan / Mobile-Charger
Mobile Charger project using Verilog in Xilinx Vivado targeting the Basys3 FPGA Board
vivado verilog fpga basys3
Language:Verilog 2
MirariFang / Basys3_Enigma_Machine
A naive implementation of an enigma machine on Basys3.
basys3 verilog fpga
Language:Verilog 2
neelabhro / FSM-Verilog-
Door Lock with provision to set the password in Real Time
fsm-library verilog fpga basys3 diligent xilinx-vivado finite-state-machine door-lock
Language:Verilog 2
neelabhro / Multiplier-
verilog basys3 fpga
Language:Verilog 2
Shubhayu-Das / VL504-project
Displaying images taken from an OV7670/laptop camera
vga basys3 ov7670 uart-verilog
Language:Python 2
ufukpalpas / Cellular-automata-game
An cellular automata game for a 8x8 matrix on the BetiBoard. (requires Basys3 board)
systemverilog vivado xilinx basys3 basys3-fpga cellular-automata
Language:SystemVerilog 2

basys3

Gowtham1729 / Image-Processing

tongplw / HW-Syn-Lab

j3soon / Handwritten-Digit-Recognition-Painter

martinKindall / risc-v-single-cycle

tongplw / Undertale-Verilog

CynicalApe / BASYS3-PONG

chili-chips-ba / openXC7-TetriSaraj

martinKindall / mips_cpu

bilalkabas / Basys3-VHDL-Basics

raleighlittles / Applied_Digital_Logic_Exercises_Using_FPGAs

soundjuice / Basys3-Pulse-Generator

Maneesh3 / Morse_Code_Encoder_Basys3

romybompart / Basys3-clock-alarm-with-buzzer

antimattercorrade / Color_Detection_BASYS3

CankutBoraTuncer / Bilkent-EEE102-Labs

meiniKi / logIP

ColtonBeery / Digital_Clock

DeanDev94 / FPGA-Audio-Effects-System

Prajjv / RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

vinayak1998 / Reflex-Tester

aliasgharchakera / flappy-bird

bingsen0806 / EE2026

ColtonBeery / Basys3_Camera_Driver

neelabhro / Complex-Adder-with-SSD

praveenVnktsh / Hardware-Accelerated-Motion-Estimation-using-FSBM-and-FPGA

raleighlittles / Basys3CountdownClock

segocago / CS223-Digital-Design-Highway-Racing

yalchinAlv / MarbleMazeGame

aryan-programmer / axi_gen_and_sum_primes_fpga

chclau / basys3_Magellan

MaxwellSiyuan / Mobile-Charger

MirariFang / Basys3_Enigma_Machine

neelabhro / FSM-Verilog-

neelabhro / Multiplier-

Shubhayu-Das / VL504-project

ufukpalpas / Cellular-automata-game