vexriscv

There are 1 repository under vexriscv topic.

• f4pga-examples

  chipsalliance / f4pga-examples

  Example designs showing different ways to use F4PGA toolchains.

  fpgafpga-designsvexriscvlitexconda-packagessymbiflow-toolchainsverilogf4pga
  Language:Verilog 261

• efabless / caravel

  Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

  caravelmagicopenramopenroadpicorv32sky130vexriscvyosys
  Language:Verilog 259

• BLangOS / VexRiscV_with_HW-GDB_Server

  VexRiscV system with GDB-Server in Hardware

  microcontrollervhdlfpga-socvexriscvgdbserverrspwishbonec-languagerisc-v
  Language:VHDL 19

• xThaid / fpga-lb

  A toy L4 load balancer running on FPGA

  fpganetworkingquartusfreertoshardcamlocamlvexriscvverilatorload-balancerdataflowriscv
  Language:C 14

• jmio / ECP5_Brieysoc

  Briey SoC on ECP5 (ICESugar Pro)

  vexriscvecp5icesugaricesugar-prorisc-v
  Language:Verilog 8

• jmio / testvex

  Briey SoC on Sipeed Tang Primer

  vexriscvsipeed-tang-primerrisc-v
  Language:Verilog 4

• mcejp / Poly94

  Yet another faux-retro game system

  cocotbfpgaprjtrellisulx3svexriscvyosys
  Language:Verilog 2

• neunzehnhundert97 / VexRiscv-Instruction-Framework

  A small framework to simplify the creation of custom instruction for the VexRiscv.

  risc-vvexriscv
  Language:Scala 2

• lnis-uofu / OpenFPGA-Softcores

  Co-architect 32-bit open-source RISC-V soft-cores for improved FPGA implementations

  openfpgavexriscvpicorv32ibex
  Language:Python 1

• supleed2 / EIE4-FYP

  Source files and notes of my Final Year Project, as part of an MEng in Electronics and Information Engineering from Imperial College London

  audio-synthesiscan-buscordicecp5embedded-systemslitexorangecrabrisc-vstacksynthsystemverilogvexriscvwaveform-generator
  Language:Python