RSPwFPGAs

opae-xilinx

OPAE porting to Xilinx FPGA devices.

qemu-hdl-cosim

VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs

virtio-fpga

A platform for emulating Virtio devices with FPGAs

virtio-fpga-bridge

Virtio front-end and back-end bridge, implemented with FPGA.

DPU-PYNQ-Ultra96v2

This repository contains the procedures and files for NN model quantization and deployment with Vitis-AI on DPU-PYNQ for Ultra96v2.

data-parallel-CPP

Source code for 'Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL' by James Reinders, Ben Ashbaugh, James Brodman, Michael Kinsner, John Pennycook, Xinmin Tian (Apress, 2020).

ixy

A simple yet fast user space network driver for Intel 10 Gbit/s NICs written from scratch

opae-xilinx-example-afu

Example AFUs based on opae-xilinx

SkyNet

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

briscv

CuckooHashingHLS

HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/

DPU-PYNQ

DPU on PYNQ

Edge-AI-Platform-Tutorials

Tutorials for the Edge AI Platform

finn

Fast, Scalable Quantized Neural Network Inference on FPGAs

huaweicloud-fpga

The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

incubator-tvm

Open deep learning compiler stack for cpu, gpu and specialized accelerators

p4fpga

P4-14/16 Bluespec Compiler

parser-gen

Network packet parser generator

pcie_screamer

PCIe Screamer - TLPs experiments...

pcileech

Direct Memory Access (DMA) Attack Software

pcimem

Simple program to read & write to a pci device from userspace

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

ReActNet

ReActNet: Towards Precise Binary NeuralNetwork with Generalized Activation Functions. In ECCV 2020.

s6_pcie_microblaze

PCI Express DIY hacking toolkit for Xilinx SP605

SkrSkr

verilog-pcie

Verilog PCI express components

virtio

Virtio implementation in SystemVerilog

XVC_PCIe_KCU105_PR

ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.